DESIGN OF

LOW
POWER TP
USING LP-

IN THIS PRESENTATION

Applications and importance

Objectives
Microwind software
DSCH
Circuits design
Stick and Layout diagrams
Processing
Future scope

IMPORTANCE

LFSR circuits are used in Built in Self Test(BIST)

structures which are used for testing of VLSI
circuits.
BIST is a Design-for-Testability (DFT) technique,
because it makes the electrical testing of a chip
easier, faster, more efficient, and less costly.
For any integrated circuit, testing is the main
criteria , in testing mode more power is
consumed so, this power is reduced by adding
extra circuit.

APPLICATIONS

Used as counters as the repeating

sequences of states of an LFSR allows it
to be used as a clock divider or counter.
Used in cryptography.
Used in test pattern generators.

OBJECTIVES

This project introduces a new test pattern generator Low Power- Linear
Feedback Shift Register (LP-LFSR) in place of conventional Linear
Feedback Shift Register(LFSR)which is more suitable for built in self
test(BIST) structure used for testing of VLSI circuits.
The new approach entails inserting 3 intermediate outputs between
every two successive outputs. The total number of signal transitions
between these 5 outputs is equal to the total number of signal
transitions between the 2 successive outputs generated using the
conventional approach.
The low power BIST technique relays on gated clock scheme for the
Psuedo random test pattern generator.
The power consumed in the TPG is minimized since only half of the Dflipflops in LP-LFSR can be activated in a given time interval.
The correlations between the consecutive patterns are higher during
normal mode than during testing. The transition is reduced by
increasing the correlation between the successive bits.
The reduction in power is due to the introduction of R-Injector circuit
which uses the concept of reducing the transitions in the test pattern
generated by conventional LFSR.

REQUIREMENTS

Microwind software to convert the

circuit into stick and layout diagrams
through which we can obtain power.

BIST(BUILT-IN-SELF-TEST)

BIST is a hierarchical DFT strategy that reduces the need for

external test. With BIST a micro-tester complete with a pattern
generator is brought onto the chip enabling the chip to test
itself.
Although the micro-tester requires more silicon area, the
savings realized through automation of the testing process
makes this DFT method very attractive.
BIST logic is composed of pattern generation, pattern capture
and compare and self test control. BIST can be used for low
speed as well as high speed testing.
BIST uses on-chip controllers for memory, logic, etc. These
controllers are typically accessed via an external interface
defined by the various IEEE standards.
The benefits of BIST are higher quality testing, faster time to
market and lower costs. Chips can be tested at speed without
incurring yield losses because of tester inaccuracy.
BIST automates a higher degree of the test development

BIST ARCHITECTURE

A typical BIST architecture consists of Test Pattern Generator

(TPG) usually implemented as a LFSR, Test Response Analyzer
(TRA), Multiple Input Signature Register (MISR), CUT and BIST
control unit as shown in the above figure.
CUT: It is the portion of the circuit tested in BIST mode. It can
be sequential, combinational or a memory. Their Primary Input
(PI) and Primary output (P0) delimit it.
TPG: It generates the test patterns for the CUT. It is dedicated
circuit or a microprocessor. The patterns may be generated in
pseudorandom or deterministically.
MISR: It is designed for signature analysis, which is a
technique for data compression. MISR efficiently map different
input streams to different signatures with every small
probability of alias.
TRA: It will check the output of MISR & verify with the input of
LFSR & give the result as error or not.
BIST Control Unit: Control unit is used to control all the

CONTRIBUTION BY EACH MEMBER

D Flip flop and R-Injector layout and output

by Shyamala
Conventional lfsr layout and output by
Bharati and Eshwari.
Modified 8-bit lfsr by Tejaswini and Kethana

LP-LFSR CIRCUIT DIAGRAM

DSCH TOOL
The DSCH program is a logic editor and simulator. DSCH is used to
validate the architecture of the logic circuit before the microelectronics
design is started. DSCH provides a user-friendly environment for
hierarchical logic design, and fast simulation with delay analysis, which
allows the design and validation of complex logic structures.
Immediate access to symbol properties

MICROWIND SOFTWARE
The

Microwind Software consists of the following tools:

MicrowindTool
DSCHTool
SiliconTool

Microwind is a tool for designing and simulating circuits at layout

level.The tool features full editing
facilities(copy,cut,past,duplicate,move)
Various views(MOS characteristics,2Dcrosssection,3Dprocessviewer),
and an analog simulator.
DSCH is a software for logic design.Based on primitives, a hierarchical
circuit can be built and simulated.It also includes delay and power
consumption evaluation.

MICROWIND TOOL HOMEPAGE

DSCH TOOL HOMEPAGE

STICK DIAGRAMS

VLSI design aims to translate circuit concepts onto

silicon.
stick diagrams are a means of capturing
topography and layer information using simple
diagrams.
Stick diagrams convey layer information through
colour codes (or monochrome encoding).
Acts as an interface between symbolic circuit and
the actual layout.

N+

16

STICK DIAGRAMS
VDD

VDD
X

X
Gnd

Gnd
17

D-FLIP FLOP

OUTPUT OF D-FLIP FLOP

R-INJECTOR CIRCUIT

OUTPUT OF R-INJECTOR CIRCUIT

CONVENTIONAL LFSR

OUTPUT OF CONVENTIONAL LFSR

MODIFIED LFSR

OUTPUT OF MODIFIED LFSR

COMPARISON BETWEEN TWO LFSRS

Conventional lfsr power is 0.62mW

whereas for modified lfsr the power
consumption is 0.255mW.
The power reduced due to R-Injector
circuit is 41.12%.

FUTURE SCOPE

In this proposed architecture the power is

reduced to
mW .In future this can be
reduced further by doing modifications in the
proposed architecture.

K
N
A
TH

U
YO