Modern Era of

Transistors(22nm
)
Sonam Kumari
II Year III Semster

Moore's law

Moore's Law
Definition
Moore's law is the observation that, over the
history of computing hardware, the number of
transistors in a dense integrated circuit
doubles approximately every two years

history

Transistor inventors

William shockley

Brattain walter houser

John bardeen

The Inventions that changed the way

computers are built
19461- The Transistor The most significant
single invention of the modern era.
3 scsientists at At&Ts Bell Labs.
Transistors are smaller (sometimes
microscopic) * Fast and dont need to warm
up

First transistor

The first point contact transistor

made by the Shockley team at Bell
Labs in 1947. DOB : December 16,
1947

Generations
Processors, Microprocessors Generations

1st Generation
8086 and 8088

80186

nd

Generation

3rd Generation
All 386 had internal 32bit
registers
386DX the first introduced by
Intel
386SX cheaper version of DX
with 24bit memory addressing
(up to 16MB rather than 4GB)
386SL laptop version of 386
80386 Coprocessor without
synchronization
issues worked with the same
clock speed.

4th Generation

4th Generation
It was the first fully pipelined processor
Fetching, decoding, execution, memory
access and writing back the results were
happening simultaneously but for different
instructions.

4th Generation
Every two clock cycles the instruction
execution was being finished.
Level 1 cache with 90-95% hit ratio.
In some versions built-in math coprocessor
Clock speed ranging from 16MHz to
133MHz, but processors could work with
any lower speed than the maximum one
given.

5th Generation

5th Generation
First Complex Instruction Set Computer(CISC)
implementing superscalar technology.
The first Pentium processor contained two pipelines
called U and V.
The pipeline U could execute any instruction. V could
execute only the most basic ones.
Behaved like two 486 processors sharing registers
and bus, executing the same program.
Every cycle was executed about one instruction. But
at around 20-30% of time there were executed two
instructions at the same time.

6th Generation
The 686 processors represent a new generation with
features not found in the previous generation units.
All started using the same basic 686 core processor
as the Pentium Pro released already in 1995.
New features
Dividing the CISC instructions into RISC instructions
(microinstructions)
Executing them multiple execution units. Parallel and
out of the initial order.
Execution speculation
Advanced branch prediction

7th Generation
Pentium 4
Introduced in 2000, started from 0,18
micrometers at 1.3GHz and reached 0.09
micrometers technology running 3.8GHz
Introduced new sets of SSE instructions: SSE2
and SSE3
L1 cache of 8 to 16kB, L2 cache up to 1MB
Hyper Threading Simulating two processors
in the system (virtual processor). Lets two
threads to really run at the same time
(without time division).

7th Generation
Pentium 4
The Pentium 4 cores had the following
codenames:
Willarnette the first one
Northwood there could be differed Mobile
and

Mobile Pentium 4 M versions

Gallatin also know as Extreme Edition with
2MB of L3 cache.
Prescott and Prescott 2M (Extreme Edition)
with 64bit instructions.

8th Generation 64bit

processors
The first 64bit processor was released in
2001 by Intel Itanium. One year later it
improved it to Itanium 2.
In 2003 AMD released Athlon 64 and later
Opteron for servers use.
In 2004 Intel released versions of Pentium 4
that were having 64bit instructions.

Dual core
processors - Intel
Intel Core Duo released at the beginning of 2006
is 32bit processor with dual core.
Has 2MB L2 cache shared between two cores.
Contains arbiter that controls access to system
bus and cache.
Intel was announcing that future versions will
have option of switching off one of the cores to
save power.
The first Intel processor used in Apple
computers.

Dual core
processors - Intel
Core 2 Duo was released in the middle of
2006.
Basically it is the 64bit version of Core Duo
Outperformed the Pentium processor family
Different versions available
Single core / Single core Extreme Edition
Dual core / Dual core Extreme Edition
Quad core / Quad core Extreme Edition

Intel Core processor

family
4nd Gen Intel Core i7 Extreme Edition
4rd Gen Intel Core i7 processor
4rd Gen Intel Core i5 processor
4rd Gen Intel Core i3 processor
4nd Gen Intel Core vPro

4nd Gen Intel Core i7 Extreme Edition

I7-5960X
Eight execution cores in one physical processor with Hyper
Threading

16 Processing Threads., Architecture 22 nm technology, 20 MB Intel

Smart Cache, Intel 64 architecture

L1 Cache: 16KB data cache

each core includes an Execution Trace Cache that stores up to 12K

decoded micro-ops in the order of program execution

L2 Cache Smart Cache dividing up 20MB between 8 cores.

Clock Speed 3.0

Up to 3.5 Ghz with Intel Turbo Boost Technology

64GB of addressable memory with DDR4 1333/1600/2133 4

channels.

Core i7 processor
technologies:
Intel Turbo Boost technology

maximizes speed for demanding applications, dynamically

accelerating performance to match your workloadmore
performance when you need it the most.

Intel Smart Cache

provides a higher-performance, more efficient cache subsystem.

Optimized for industry leading multi-threaded games.

Intel QuickPath Interconnect

designed for increased bandwidth and low latency. It can achieve

data transfer speeds as high as 25.6 GB/sec with the Extreme
Edition processor.

Intel HD Boost

significantly improves a broad range of multimedia and computeintensive applications. The 128-bit SSE instructions are issued at
a throughput rate of one per clock cycle, allowing a new level of
processing efficiency with SSE4 optimized applications.

4th Intel Core i5

Processor

Two or Four execution cores in one physical processor .

Architecture 22 nm technology

3 to 6 MB Intel Smart Level 3 Cache

Intel 64 architecture

L1 Cache: 16KB data cache

each core includes an Execution Trace Cache that stores up to 12K

decoded micro-ops in the order of program execution

L2 Cache 4X 256KB

Clock Speed 2.8 to 3.8 GHz

8 to 32GB of addressable memory with DDR3 1333/1600
Dual channel.

~$200

Intel Core i3 Processor

Two execution cores in one physical processor,

executions threads.

Architecture 22 nm technology

3 to 4MB Intel Smart Cache

Intel 64 architecture

17 to 55W

L1 Cache: 16KB data cache

each core includes an Execution Trace Cache that stores up to 12K decoded
micro-ops in the order of program execution

L2 Cache 2X 256KB

Clock Speed 3.1to 3.8 GHz

8 to 32GB of addressable memory with DDR3 1333/1600 Dual
channel.

Priced between $100 to $150 (where the 2.1Ghz processor at 35W)

Generation Intel Core

vPro Processor Family
Add on to the i7 and i5 processors.
You can also help protect your organizations
sensitive data with optional Intel Anti-Theft
Technology (Intel AT).

Intel Anti-Theft Technology (Intel AT) for

Laptop Security.

Processes

45 nm Process.
32 nm Process.
Difference between 65 45 -32 nm Process.

Advantages of smaller transistor.

Demits or Challenges of smaller transistor.

22nm Process.

45nm Process
Per the International Technology Roadmap
for Semiconductors, the 45 nanometer (45
nm) technology node should refer to the
average half-pitch of a memory cell
manufactured at around the 20072008
time frame.
Chipmakers have initially voiced concerns
about introducing new high-k materials into
the gate stack, for the purpose of reducing
leakage current density.

45nm Process Specs

lithography is used.
Properties
160 nm gate pitch (73% of 65 nm generation)
200 nm isolation pitch (91% of 65 nm
generation) indicating a slowing of scaling of
isolation distance between transistors
Extensive use of dummy copper metal and
dummy gates
35 nm gate length (same as 65 nm generation)
1 nm equivalent oxide thickness, with 0.7 nm
transition layer
Gate-last process using dummy polysilicon and
damascene metal gate
Squaring of gate ends using a second
photoresist coating

32 nm Process
The 32 nanometer (32 nm) node is
the step following the 45 nanometer
process in CMOS semiconductor
device fabrication. "32 nanometer"
refers to the average half-pitch (i.e.,
half the distance between identical
features) of a memory cell at this
technology level.Intel began selling
its first 32 nm processors using the
Westmere architecture on 7 January
2010.
The 32 nm process was superseded
by commercial 22 nm technology in
2012.

65 v/s 45 v/s 32 nm

32 AND 45nm

22nm 3D/Tri-gate
Transistors Process
Fabrication Process

Step 1

Sand
Silicon is the second most abundant element in the earth's
crust. Common sand has a high percentage of silicon.
Silicon the starting material for computer chips is a
semiconductor, meaning that it can be readily turned into
an excellent conductor or an insulator of electricity, by the
introduction of minor amounts of impurities.

Step 2

Melted Silicon
scale: wafer level (~300mm / 12 inch)
In order to be used for computer chips, silicon must be
purified so there is less than one alien atom per billion. It is
pulled from a melted state to form a solid which is a single,
continuous and unbroken crystal lattice in the shape of a
cylinder, known as an ingot.

Step 3

Monocrystalline Silicon Ingot

scale: wafer level (~300mm / 12 inch)
The ingot has a diameter of 300mm and weighs about 100
kg.

Step 4

Ingot Slicing
scale: wafer level (~300mm / 12 inch)
The ingot is cut into individual silicon discs called wafers.
Each wafer has a diameter of 300mm and is about 1 mm
thick.

Step 5

Wafer
scale: wafer level (~300mm / 12 inch)
The wafers are polished until they have flawless, mirrorsmooth surfaces. Intel buys manufacturing- ready wafers
from its suppliers. Wafer sizes have increased over time,
resulting in decreased costs per chip. when Intel began
making chips, wafers were only 50mm in diameter. Today
they are 300mm, and the industry has a plan to advance
to 450mm.

Step 6

Applying Photoresist
scale: wafer level (~300mm / 12 inch)
Photolithography is the process by which a specific pattern
is imprinted on the wafer. It starts with the application of a
liquid known as photoresist, which is evenly poured onto
the wafer while it spins. It gets its name from the fact that
it is sensitive to certain frequencies of light (photo) and
is resistant to certain chemicals that will be used later to
remove portions of a layer of material (resist).

Step 7

Exposure
scale: wafer level (~300mm / 12 inch)
The photoresist is hardened, and portions of it are exposed to
ultraviolet (UV) light, making it soluble. The exposure is done
using masks that act like stencils, so only a specific pattern of
photoresist becomes soluble. The mask has an image of the
pattern that needs to go on the wafer; it is optically reduced by
a lens, and the exposure tool steps and repeats across the wafer

Step 8

Resist Development
scale: wafer level (~300mm / 12 inch)
The soluble photoresist is removed by a chemical process,
leaving a photoresist pattern determined by what was on
the mask.

Step 9

Resist Development
The wafer with patterned photoresist is bombarded with a
beam of ions (positively or negatively charged atoms)
which become embedded beneath the surface in the
regions not covered by photoresist.

Step 10

Removing Photoresist
scale: wafer level (~300mm / 12 inch)
After ion implantation, the photoresist is removed and the
resulting wafer has a pattern of doped regions in which
transistors will be formed.

Step 11

Begin Transistor Formation

scale: transistor level (~50-200nm)
Here we zoom into a tiny part of the wafer, where a single
transistor will be formed. The green region represents
doped silicon. Todays wafers can have hundreds of billions
of such regions which will house transistors.

Step 12

Etch
scale: transistor level (~50-200nm)
In order to create a fin for a tri-gate transistor, a pattern of
material called a hard mask (blue) is applied using the
photolithography process just described. Then a chemical
is applied to etch away unwanted silicon, leaving behind a
fin with a layer of hard mask on top.

Step 13

Removing Photoresist
scale: transistor level (~50-200nm)
The hard mask is chemically removed, leaving a tall, thin
silicon fin which will contain the channel of a transistor.

Step 14

Silicon Dioxide Gate Dielectric

scale: transistor level (~50-200nm)
Using a photolithography step, portions of the transistor
are covered with photoresist and a thin silicon dioxide
layer (red) is created by inserting the wafer in an oxygenfilled tube-furnace. This becomes a temporary gate
dielectric.

Step 15

Polysilicon Gate Electrode

scale: transistor level (~50-200nm)
Again using a photolithography step, a temporary layer of
polycrystalline silicon (yellow) is created. This becomes a
temporary gate electrode.

Step 16

Insulator
scale: transistor level (~50-200nm)
In another oxidation step, a silicon dioxide layer is created
over the entire wafer (red/transparent layer) to insulate
this transistor from other elements.

Step 17

Removal of Sacrificial Gate

scale: transistor level (~50-200nm)
Using a masking step, the temporary (sacrificial) gate
electrode and gate dielectric are etched away. The actual
gate will now be formed; because the first gate was
removed, this procedure is known as gate last.

Step 18

Applying High-k Dielectric

scale: transistor level (~50-200nm)
Individual molecular layers are applied to the surface of
the wafer in a process called atomic layer deposition.
The yellow layers shown here represent two of these.
Using a photolithography step, the high-k material is
etched away from the undesired areas such as above the
transparent silicon dioxide.

Step 19

Metal Gate
scale: transistor level (~50-200nm)
A metal gate electrode (blue) is formed over the wafer
and, using a lithography step, removed from regions other
than where the gate electrode is desired. The combination
of this and the high-k material (thin yellow layer) gives the
transistor much better performance and reduced leakage
than would be possible with a traditional silicon
dioxide/polysilicon gate.

Step 20

Ready Transistor
scale: transistor level (~50-200nm)
This transistor is close to being finished. Three holes have
been etched into the insulation layer (red color) above the
transistor. These three holes will be filled with copper or
other material which will make up the connections to other
transistors.

Step 21

Electroplating
scale: transistor level (~50-200nm)
The wafers are put into a copper sulphate solution at this
stage. The copper ions are deposited onto the transistor
thru a process called electroplating. The copper ions travel
from the positive terminal (anode) to the negative terminal
(cathode) which is represented by the wafer.

Step 22

After Electroplating
scale: transistor level (~50-200nm)
On the wafer surface the copper ions settle as a thin layer
of copper.

Step 23

Polishing
scale: transistor level (~50-200nm)
The excess material is mechanically polished away to
reveal a specific pattern of copper.

Step 24

Metal Layers
scale: transistor level (six transistors combined ~500nm)
Multiple metal layers are created to interconnect (think:
wires) all the transistors on the chip in a specific
configuration.

Step 25

Wafer Sort
scale: die level (~10mm / ~0.5 inch)
This portion of a ready wafer is being put through a test. A
tester steps across the wafer; leads from its head make
contact on specific points on the top of the wafer and an
electrical test is performed.

Step 26

Wafer Slicing The wafer is cut into pieces (called die).

The above wafer contains future Intel processors
codenamed Ivy Bridge.
Selecting Die for Packaging The die that responded
with the right answer to the test patterns will be packaged.

Step 27

Packaging
The chip is packages into processor sockets designed to
connect all connectors to motherboard when installed on
the top of motherboard. With a case cum metal heatsink.

Microarchitecture
Relation to instruction set architecture
Single bus organization microarchitecture
Aspects of microarchitecture
Intel 80286 microarchitecture
Increasing execution speed
Instruction set choice
Instruction pipelining
Cache
Branch prediction
Superscalar
Out-of-order execution
Register renaming
Multiprocessing and multithreading.

Smaller Transistor
Benefits for
Software
development