Logic and Sequential Circuit

Design
(EC 201)

Textbook

Digital Logic and Computer

Design by M. Morris Mano (Jan
2000 )

Topics

Boolean Algebra and Logic Gates:

Binary Logic and Gates, Boolean Algebra
and Functions, Canonical and Standard
Forms, Logic Operations, Digital Logic
Gates, and IC Digital Families.
Simplification of Boolean Functions: KMap Method and Simplification using
Different Variables Map, Simplification of
Product of Sums, Implementation with
NAND and NOR Gates, Dont Care
Conditions, The Tabulation Method,
Determination of Prime-Implicants, and
Selection of Prime-Implicants.

Continue

Combinational Logic Design: Design

Procedure, Adders, Subtractors, Code
Conversion, Analysis Procedure, Multilevel
NAND Circuits, Multilevel NOR Circuits,
Exclusive-OR, and Equivalence Functions
Combinational Logic with MSI and
LSI: Decimal Adder, Magnitude
Comparator, Decoders, Encoders,
Multiplexers, Demultiplexers, Binary
Adders, Binary Subtraction, Binary AdderSubtractors, Binary Multipliers and HDL
Representation VHDL/Verilog

Continue
Sequential Logic/Circuits: Latches, FlipFlops, Triggering of Flip-Flops, Clocked
Sequential Circuits and their Analysis,
State Reduction and Assignment, Flip-Flop
Excitation Tables, Design Procedure,
Designing with D & JK Flip-Flops,
HDL/Verilog Representation for a
Sequential Circuits VHDL/Verilog

Boolean Algebra
&
Logic Gates

Common Postulates (Boolean Algebra)

Closure
N={1,2,3,4,5,..}
It is closed w.r.t +
i.e. a+b=c
as a,b,cN
Associative Law
(x*y)*z = x*(y*z)
for all x,y,z,S
Commutative Law
x*y = y*x for all x,yS
x+y = y+x
x+y = y+x
x.Y = y.x

Common Postulates (Boolean Algebra)

Identity Element
e*x = x*e = x
x+0 = 0+x = x
e+x = x+e = x
x.1 = 1.x = x
0+x = x+0 = x
1*x = x*1 = x
Inverse
x+x = 1 x*y = e a*1/a = 1
x.x = 0 x+y = e
a+(-a) = 0
Distributed Law
x*(y.z) = (x*y) . (x*z)
x.(y+z) = (x.y) + (x.z)
x+(y.z) = (x+y) . (x+z)

xS

Boolean Algebra and Logic Gates

x

x.y

x+y

x.(y+z) = (x.y)+(x.z)
x

Y+z

x.(y+z)

x.y

x.z

(x.y)+x.z

Postulates and Theorems of Boolean

Algebra
Postulate 2

(a) x+0 = x

(b) x.1 = x

Postulate 5

(a) x+x = 1

(b) x.x = 0

Theorem 1

(a) x+x = x

(b) x.x = x

Theorem 2

(a) x+1 = 1

(b) x.0 = 0

Theorem3, involution

(x) = x

Postulate3, commutative

(a) x+y = y+x

(b) xy = yx

Theorem4, associative

(a) x+(y+z)=(x+y)+z

(b) x(yz) = (xy)z

Postulate4, distributive

(a) x(y+z)=xy+xz

(b) x+yz = (x+y)(x+z)

Theorem5, DeMorgan

(a) (x+y) = xy

(b) (xy) = x+y

Theorem6, absorption

(a) x+xy = x

(b) x(x+y)=x

Theorems
1a.

1b.

x+x = x
x+x = (x+x).1
= (x+x)(x+x)
= x+xx
=x+0
=x
x.x = x (Remember Duality of 1a)
x.x = xx+0
= xx+xx
= x(x+x)
= x.1
=x

Theorems
2a. x+1 = 1
x+1 =1.(x+1)
= (x+x)(x+1)
= (x+x)
= x+x
=1
2b. X.0 = 0 (Remember Duality of
of 2a)

3.

(x) = x
Complement of x = x
Complement of x = (x) = x
6a x+xy = x
x+xy = x.1+xy
= x(1+y)
= x.1
=x
6b. x(x+y) = x (Remember Duality of 6a)
Can also be proved using truth table
method

xy

x+xy

x=x+xy
x

x+y

(x+y)

xy

(x+y) = xy DeMorgans Theorem

(xy) = x +y DeMorgans Theorem

Operator Precedence
1.( )
2.NOT
3.AND
4.OR

y
xy

xy

xy

xy
VENN DIAGRAM FOR TWO VARIABLES

VENN DIAGRAM ILLUSTRATION X=XY+X

z
x+(y+z)

xy+xz
VENN DIAGRAM ILLUSTRATION OF THE DISTRIBUTIVE LAW

TRUTH TABLE FOR F1=xyz, F2=x+yz, F3=xyz+xyz+xy

and F4=xy+xz
x

F1

F2

F3

F4

z
x
y

F1

F2

y
z

(a) F1 = xyz

(b) F2 = x+yz

F3

(c) F3 = xyz+xyz+xy

x
y

F4

(c) F4 = xy+xz

Implementation of Boolean Function with GATES

Algebraic Manipulations for Minimization of Boolean

Functions
(Literal minimization)

1.
2.
3.
4.

5.

x+xy = (x+x)(x+y)
= 1.(x+y)=x+y
x(x+y) = xx+xy
= 0+xy=xy
xyz+xyz+xy
= xz(y+y)+xy
= xz+xy
xy+xz+yz
(Consensus Theorem)
=xy+xz+yz(x+x)
=xy+xz+xyz+xyz
=xy(1+z)+xz(1+y)
=xy+xz
(x+y)(x+z)(y+z)=(x+y)(x+z)
by duality from function 4

Complement of a Function
(A+B+C) = (A+X)
= AX
= A.(B+C)
= A.(BC)
= ABC
(A+B+C+D+..Z) = ABCD..Z
(ABCD.Z) = A+B+C+D+.+Z
Example using De Morgans Theorem (Method-1)
F1 = xyz+xyz
F1 = (xyz+xyz)
= (x+y+z)(x+y+z)
F2 = x(yz+yz)
F2= [x(yz+yz)]
= x+(y+z)(y+z)

Example using dual and

complement of each literal
(Method-2)

F1 = xyz + xyz

Dual of F1 = (x+y+z)(x+y+z)
Complement F1 = (x+y+z)
(x+y+z)
F2 = x(yz+yz)
Dual of F2=x+[(y+z)(y+z]
Complement =F2= x+ (y+z)(y+z)

Minterm or a Standard Product

n variables forming an AND term provide 2n
possible combinations, called minterms or
standard products (denoted as m1, m2 etc.).
Variable primed if a bit is 0
Variable unprimed if a bit is 1
Maxterm or a Standard Sum
n variables forming an OR term provide 2n
possible combinations, called maxterms or
standard sums (denoted as M1,M2 etc.).
Variable primed if a bit is 1
Variable unprimed if a bit is 0

MINTERMS AND MAXTERMS FOR THREE BINARY

VARIABLES
MINTERMS

MAXTERMS

Term

Designation

Term

Designation

xyz

m0

x+y+z

M0

xyz

m1

x+y+z

M1

xyz

m2

x+y+z

M2

xyz

m3

x+y+z

M3

xyz

m4

x+y+z

M4

xyz

m5

x+y+z

M5

xyz

m6

x+y+z

M6

xyz

m7

x+y+z

M7

FUNCTION OF THREE VARIABLES

x

Function f1

Function f2

f1 = xyz+xyz+xyz
=m1 + m4 + m7
f2 = xyz+xyz+xyz+xyz = m3 + m5 + m6 + m7

MINTERMS AND MAXTERMS FOR THREE BINARY

VARIABLES

f1 = xyz+xyz+xyz
f1 = xyz+xyz+xyz+xyz+xyz
f1 =(x+y+z)(x+y+z)(x+y+z)(x+y+z) (x+y+z)
= M0.M2.M3.M5.M6
= M0M2M3M5M6
f2 = xyz+xyz+xyz+xyz
f2 = xyz+xyz+xyz+xyz
f2 = (x+y+z)(x+y+z)(x+y+z)(x+y+z)
= M0 M1 M2 M4
Canonical Form
Boolean functions expressed as a sum of minterms or
product of maxterms are said to be in canonical form.
M3+m5+m6+m7 or
M0 M1 M2 M4

Sum of Minterms (Sum of

Products)

Example:
F = A+BC
F = A(B+B)+BC(A+A)
= AB+AB+ABC+ABC
= AB(C+C)+AB(C+C)+ABC+ABC
= ABC+ABC+ABC+ABC+ABC+ABC
= ABC+ABC+ABC+ABC+ABC
= m1+m4+m5+m6+m7
F(A,B,C)=(1,4,5,6,7)
ORing of term

AND terms of variables A,B &C

They are minterms of the function

Product of Maxterms (Product of

sums)

Example: F = xy+xz
F = xy+xz
F = (xy+x)(xy+z)
distr.law (x+yz)=(x+y)(x+z)
= (x+x)(y+x)(x+z)(y+z)
= (x+y)(x+z)(y+z)
= (x+y+zz)(x+z+yy)(y+z+xx)
= (x+y+z)(x+y+z)(x+z+y)(x+z+y)(y+z+x)
(y+z+x)
= (x+y+z)(x+y+z)(x+y+z)(x+y+z)
= M0 M2 M4 M5
F(x,y,z) = (0,2,4,5)

ANDing of terms Maxterms of the function (4 OR terms

of variables x,y&z)

Conversion between Canonical

Forms

F(A,B,C) = (1,4,5,6,7)
sum of minterms
F(A,B,C) = (0,2,3)
= m0+m2+m3
F(A,B,C) = (m0+m2+m3)
= m0.m2.m3
= M0 M2 M3
= (0,2,3)
Product of maxterms
Similarly
F(x,y,z) = (0,2,4,5)
F(x,y,z) = (1,3,6,7)

Standard Forms
Sum of Products (OR operations)
F1 = y+xy+xyz
(AND term/product term)
Product of Sums (AND operations)
F2=x(y+z)(x+y+z+w)
(OR term/sum term)
Non-standard form
F3=(AB+CD)(AB+CD)
Standard form of F3
F3=ABCD + ABCD

TRUTH TABLE FOR THE 16 FUNCTIONS

OF TWO BINARY VARIABLES
x

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

F11

F12

F13

F14

F15

Operator
symbols

F0 = 0

F1 = xy

F2 = xy

F3 = x

F4 = xy

F5 = y

F6 = xy +xy

F7= x +y

F8 = (x+y)

F9 = xy +xy

F10 = y

F11 = x +y

F12 = x

F13 = x + y

F14 = (xy)

F15 = 1

BOOLEAN EXPRESSIONS FOR THE 16 FUNCTIONS OF TWO

VARIABLE
BOOLEAN
FUNCTIONS

OPERATOR
SYMBOL

NAME

F0 =0

COMMENTS

NULL

BINARY CONSTANT 0

F1=xy

x.y

AND

F2=xy

x/y

inhibition

F3=x
F4=xy
F5=y
F6=xy+xy
F7=x+y
F8=(x+y)
F9=xy+xy
F10=y
F11=x+y
F12=x
F13=x+y
then y
F14=(xy)

transfer
inhibition
transfer
exclusive-OR
OR
NOR

y/x
x
y
x+y
x
y
x
y
x

x and y

x
y but not x
y
x or y but not both
x or y
not OR

*equivalence
complement
not y
implication
complement
implication

xy
xy
x

x but not y

NAND

x equals y
if y then x
not x
if x
not AND

 *Equivalence is also known as equality, coincidence,

and exclusive NOR
16 logic operations are obtained from two variables x
&y
Standard gates used in digital design are: complement,
transfer, AND, OR , NAND, NOR, XOR & XNOR
(equivalence).

H and L LEVEL IN IC LOGIC

FAMILIES
IC Family Voltage
High-level voltage Low-level
Type
Supply (V)
(V) voltage (V)

Range

Typical

TTL
Vcc=5
2.4-5
3.5
ECL
VEE=-5.2 -0.95- -0.7 -0.8
CMOS VDD=3--10 VDD
VDD
Positive Logic:
Logic-1
Negative Logic
Logic-0

Range

Typical

0-0.4
0.2
-1.9-- -1.6 -1.8
0-0.5
0
Logic-0
Logic-1

TYPICAL CHARACTERISTICS OF IC
LOGIC FAMILIES
IC Logic
Family
Standard TTL
Shottky TTL
Low power
Shottky TTL
ECL
CMOS

Fan out

Power
Dissipation (mw)

Propagation
delay (ns)

Noise Margin (v)

10
10

10
22

10
3

0.4
0.4

20
25
50

2
25
0.1

10
2
25

0.4
0.2
3

TTL basic circuit : NAND gate

ECL basic circuit: NOR gate
CMOS basic circuit: Inverter to construct NAND/NOR

DIGITAL LOGIC GATES

NAME

GRAPHIC
SYMBOL

AND
X
Y

TRUTH
TABLE

F=XY

X Y
0 0
0 1
1 0
1 1

F
0
0
0
1

F=X+Y

X Y
0 0
0 1
1 0
1 1

F
0
1
1
1

OR
X
Y

ALGEBRIC
FUNCTION

NAME

GRAPHIC
SYMBOL

ALGEBRIC
FUNCTION

Inverter
X

F=X

X
0
1

F
1
0

F=X

X
0
1

F
0
1

Buffer
X

NAND

X
Y

TRUTH
TABLE

F=(XY)

X Y
0 0
0 1
1 0
1 1

F
1
1
1
0

NAME

NOR

Exclusive-OR
(XOR)

Exclusive-NOR
or
Equivalence

GRAPHIC
SYMBOL
X
Y

X
Y

TRUTH
TABLE

F=(X+Y)

X Y
0 0
0 1
1 0
1 1

F
1
0
0
0

X Y
0 0
0 1
1 0
1 1

F
0
1
1
0

X Y
0 0
0 1
1 0
1 1

F
1
0
0
1

F=XY+XY
=XY

X
Y

ALGEBRIC
FUNCTION

F=XY+XY
=X Y

(X+Y)

[Z+(X+Y)]

(X

Y) Z=(X+Y) Z
=XZ+YZ

(X ( Y Z)=X(Y+ Z)

=XY+XZ
[X+(Y+Z)]
Y
Z

(Y+Z)

Demonstrating the nonassociativity of the NOR operator

(X Y) Z X (Y Z)

X
Y
Z

(X+Y+Z)

(a) There input NOR gate

X
Y
Z

(XYZ)

(b) There input NAND gate

A
B
C
F=[(ABC). (DE)]=ABC+DE
D
E

(c) Cascaded NAND gates

Multiple-input AND cascaded NOR and NAND gates

TRUTH TABLE
X
Y

F=X Y Z

(a) Using two input gates

X
Y
Z

X
0
0
0
0
1
1
1
1

Y
0
0
1
1
0
0
1
1

Z
0
1
0
1
0
1
0
1

F
0
1
1
0
1
0
0
1

1
0
0
1
0
1
1
0

XOR
F=X Y Z
XNOR
(b) Three input gates

(b) Three input exclusive OR gates

Odd
function
Even
function

IC DIGITAL LOGIC FAMILIES

TTL

Transistor- Transistor Logic

Very popular logic family.

It has a extensive list of digital functions.
It has a large number of MSI and SSI devices, also has LSI
devices.
ECL Emitter Coupled Logic

Used in systems requiring high speed operations.

It has a large number of MSI and SSI devices, also LSI devices.

MOS Metal-Oxide Semiconductor

Used in circuit requiring high component density

It has a large number of MSI and SSI devices, also LSI devices
(mostly)

CMOS Complementary MOS

Used in systems requiring low power consumption.

It has a large number of MSI and SSI devices, also has LSI
devices.

I2L Integrated - Injection Logic

Used in circuit requiring high component density.

Mostly used for LSI functions

Some Typical IC Gates

VCC
14

VCC
13

12

11 10

GND

7404 Hex Inverters

TTL gates

14 13

12

11 10

GND

7400 Quadruple 2-input

NAND gates

VCC 2
16 15

Some Typical IC Gates

14

13

12

11

10

10107 Triple
Exclusive OR/
NOR gates

1 2
VCC 1

VCC 2
16

15

14

13

12

8 VEE 2 (-5.2V)

11

10

10102 Quadruple
2-Input NOR gate

VCC 1

VEE (-5.2V)

(3-15 V)

VDD
14

13

12

NC
11

10

C MOS
GATES

4002 dual 4 input NOR gates

NC

Vss (GND)

NC

NC
16 15

14

13

12

11

10

CMOS
GATES
1

VDD

8 Vss
(GND)

(3-15 V)

4050 Hex buffer

LOGIC

SIGNAL

LOGIC

SIGNAL

VALUE

VALUE

VALUE

VALUE

Positive Logic

L
Negative Logic

Signal amplitude assignment and type of logic

Truth table in terms of

x
TTL
7400
GATE

Gate block diagram

H and L
X

Truth table for positive logic

H=1,

L=0

x
y

Graphic symbol for

positive logic NAND gate

x
y

Graphic symbol for negative logic

NOR gate

Truth table for negative logic

L=1

H=0

Same gate can function

+ive logic NAND or -ive logic NOR
+ive logic NOR or -ive logic NAND

DEMONSTRATION OF POSITIVE AND

NEGATIVE LOGIC

Characteristics of IC logic families

(parameters)
Fan-out
Specifies the number of standard loads (the amount of current
needed by an input of another gate in the same IC family) that the
output of a gate can drive without impairing its normal operation.
it is expressed by a number.
Power dissipation
It is the supplied power required to operate the gate. It is
expressed in mw.
Propagation delay
It is the average transition delay time for a signal to propagate
from input to output when the binary signals change in value. It is
expressed in ns.
Noise margin
It is the maximum noise voltage added to the input signal of a