CMOS Mask Design

Basic Overview

Jack Hong

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INTEL CONFIDENTIAL

Contents

Introduction

Preparation, planning and schedule estimation

Starting layout work

Post layout edits

Final layout stage

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Chapter 1: Introduction

What is an Integrated Circuit (IC)

Another

name for a chip, an integrated circuit (IC) is a small

electronic device made out of a semiconductor material. The first
integrated circuit was developed in the 1950s by Jack Kilby of Texas
Instruments and Robert Noyce of Fairchild Semiconductor.

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Chapter 1: Introduction

What is an Integrated Circuit (IC)

Integrated

circuits are used for a variety of devices, including

microprocessors, audio and video equipment, and automobiles.
Integrated circuits are often classified by the number of transistors
and other electronic components they contain:

SSI (small-scale integration): Up to 100 electronic components per

chip

MSI (medium-scale integration): From 100 to 3,000 electronic

components per chip

LSI (large-scale integration): From 3,000 to 100,000 electronic

components per chip

VLSI (very large-scale integration): From 100,000 to 1,000,000

electronic components per chip

ULSI (ultra large-scale integration): More than 1 million electronic

components per chip

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Chapter 1: Introduction

What is CMOS
CMOS

(complementary metal-oxide-semiconductor) logic uses a

combination of p-type and n-type metal-oxide-semiconductor field
effect transistors (MOSFETs) to implement logic gates and other
digital circuits found in computers, telecommunications and signal
processing equipment

It

is the technology of choice for many present-day digital integrated

circuits

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Chapter 1: Introduction

IC Design
Key

features: small size, high complexity, low cost, high reliability

Key

challenges: unwanted interactions caused by close proximity of

circuit components on the same chip, and power dissipation

The

process from initial planning to final silicon production can take

from months to years depending on the complexity of the design

For example, a computer CPU with 10 million transistors could take a

couple of years and hundreds of designers

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Chapter 1: Introduction

Planning

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Chapter 1: Introduction

Planning
Chip

specifications are drawn up by the system user/designer

Covers functionality, frequency of operation (speed), power dissipation,

package type, number of package pins, volume, reliability, voltage and
current ratings, etc.

Initial specification leads the designer to conclusions on the technology

and architecture to be used.

System

test considerations are taken into account to ensure

adequate and economic testing possible (e.g Design for Test, DFT)

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Chapter 1: Introduction

Implementation
Designs

are often done using a Hardware Description Language

(HDL) such as VHDL (Very High Speed IC HDL) for digital systems or
Analogue HDL for analogue or mixed analogue/digital systems.

Advantage is ease of use, and correct-by-design facility by using a

synthesis tool to generate the low-level designs.

However,

the traditional design procedure is:

Draw the circuit using a schematic capture package

Simulate the circuit using a simulator tool (logic system for digital, circuit
for analogue)

Lay out the chip using a layout package

Back-annotate the layout to check for errors and re-simulate using actual
layout parameters

Mask production from the layout

Silicon fabrication using the masks and thin slices of silicon (wafers), test
the wafers and package the chips

Production test

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Chapter 1: Introduction

How does Mask Design Fit in the Design Process?

IC Micro-Architecture
Design & Verification

IC Logic Design &

Verification

IC Circuit Design

IC Layout Design

Market research and customer inquiry collection

Basic Layout
Design
Tasks
Logic design and functionality
verification
Interpret Logic-L
Schematics

Circuit design and timing verification

Convert Logic-Le
to Transistor-Lev
Layout design and Design Schematics
Rule Verification

IC Mask Generation

Create Layout Dra

Alignment mark, from

scribe lineTransistor-L
generation, tape out
Schematics

IC Fabrication

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Chapter 1: Introduction

A detailed look at the layout design stage

IC Micro-Architecture
Design & Verification

IC Logic Design &

Verification

IC Circuit Design

Logic-Level
Schematics

Basic Layout
Design Tasks
Interpret Logic-Level
Schematics

Transistor-Level
Schematics

IC Layout Design

Convert Logic-Level
to Transistor-Level
Schematics

Layout Drawing

IC Mask Generation

Create Layout Drawing

from Transistor-Level
Schematics

Interpret schematic information

Pre-layout planning
Physical layout generation
Add post-layout objects to
enhance IC quality & reliability
Perform Design Rule
Verification
ECO implementation
Full chip assembly
Tape out celebration

IC Fabrication

First IC Silicon
R

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Chapter 2: Video

The complete Silicon Run

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Chapter 3: Preparation & Planning

Establish Teams
The

whole IC design process can take months or years

Teams

must be established for marketing, design engineering, mask

designer, assembly, tester, and sales

Establish Schedule
Each

team manager will make a schedule based on the inputs from

team members experience

The

teams schedule should be in-sync with other teams schedules

Project

manager is normally responsible for the overall coordination

Plan the Execution

Plan

best strategy for avoiding any delays

Delays

in any team will impact other teams

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Chapter 3: Planning the Layout

Schematic

Netlist

Floorplan is a high-level outline of how the major sections of the chip will be
organized and connected
Planning the dimensions of major sections, and the paths for connecting
them, is the most important role of the floorplan
Can be designed by either top-down or bottom-up planning strategy

Existing layout (design reuse)

Netlist is text version of schematic

This is the most common design input for CAD tools

Floorplan

Schematics are usually designed by circuit designers

This is the most common design input for MDs doing custom layout work

Library cells, fubs, sections are often reused from one design to another
Minor or major rework might be done to reused layout

Sketch drawing

To help estimate cell size, and plan power tracks, clock tree, critical signals,
pins, ports, and cell abutments
Sometimes done with stick figures which is quicker than drawing all the
geometries

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Chapter 3: Planning the Layout

Cell size and aspect ratio

Sketch

cell, device, pin, and port placement with stick diagrams

Consider sharing/splitting geometries across abutting cells
Reserve some room for future ECO edits
Layout devices unspecified in schematic (taps, nacs, decaps)

Sensitive and Special circuitry

Grouped/matched
Isolated

topographies

devices

Critical Signals, power grids and clock tree

Work

out their interrelationships

Net specs

Floorplan
Correlate

top-down and bottom-up plans

Layout limitations
Project

methodology guidelines

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Chapter 3: Preparation and Planning

Planning cell size and aspect ratio

Calculate

number of layout objects (device/cell)

Consider

process related design rules

Calculate

average area per transistor

Total area = X * Y

Density = total area/number of transistor

Calculate

area for layout object(s)

number of cells and the cell size

number of devices and their area

routing channels and net congestion

additional devices (taps, nacs, decaps)

Scheduling
Calculate

number of devices/cells drawn per day/week

consider CAD tool capabilities, machine/netbatch load

consider multiple iterations

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Chapter 4: Layout Work Flow

Generate the power grid, clock tree and critical signals

Interpret schematic

Compact the initial layout to meet planned/required dimensions

Layout Verification

Connect the devices & cells to the infrastructure

In GeneSys this might be done with Auto-Route, Click and Route, and PTPED

Layout area minimization

Generate corresponding layout devices & cells

In GeneSys, this might be done with SCH2L, PLACE, Family Generation,
Copy, Ptped, Move, MoveEdge

Layout interconnection

The remaining layout needs to fit within this infrastructure

Online, batch and PDS/ISS layout verification flows are used throughout the
layout work process

Check in per Layout Milestone Deadlines

Similar to checking software fixes into a weekly branch, or code freeze

Layout data is checked into the designated library daily, and also for more
major milestones

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Chapter 5: Post-Layout Work Flow

ECOs
Just like in software development, design changes and fixes are sometimes
necessary after freeze deadlines
Often are result of findings from circuit simulation and timing analysis
Includes device or cell replacement/upsizing/downsizing, and net
renaming/re-hookup

Reliability and manufacturability checks

Reliability checks are done to meet chip life expectancy requirements, which
is part of the original spec
Manufacturability checks are done to increase yields (and profits )

Layout Quality

Eliminate sources of unwanted resistance

Eliminate sources of IR drop

Notches in wires, dangling tails on wires, jogs, or scenic routing

Not enough contacts/vias, or poorly spaced/positioned contacts/vias

Chip level DRCs

Some rules (e.g. metal density) only apply at the unit or full-chip level
They can only be done after fubs are frozen and assembled

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Chapter 6: Final Layout

Layout plot review

Goal

of plot review is to give final visual check that everything is there

that needs to be there (catch anything the CAD tools may have
missed)

Critical signals, guard rings, device matching, signal shielding

Traditionally,

huge paper plots of the design are made, to allow easier

visualization of fubs, units, and full chip

Advantage of huge paper plots is you can see more than you can see
on screen

A more

modern approach is to project the design to the big-screen

Advantage of this is you can use CAD tools to make on-line annotations
of problems found in the plot review

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Chapter 6: Final Layout

Final Assembly
Division

of work common in Intel microprocessor projects

MDs are usually responsible for layout at the cell and fub level

Senior MDs are responsible for layout at the unit level

Assembly is done by a small set of senior MDs and CDs

Final Layout Verification

Usually

finds problems that only become evident after assembly

shorts/opens between units or across hierarchy, NAC and tap violations,

metal density violations

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Chapter 6: Final Layout

Scribe Lines and Alignment Marks

Information

specifically for the fab machines, to align all the layers

properly

Scribe line is an area between die, which is intentionally left empty so a

saw can pass through when sawing die apart

Alignment marks are cross-shaped targets on a reticle (mask) that are

used to line up masks vertically. Each mask layer has an alignment mark
to register it to the rest of the layers.

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Chapter 6: Final Layout

Optical Proximity Correction

Special

CAD tool adds geometries that compensate for optical effects

related to photolithography on extremely small dimensions

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Chapter 6: Final Layout

Tape Out
Layout

of the whole chip, one mask layer at a time, is sent to a

fracture program that translates the geometries into trapezoids
that the mask generation machines/software expects

Due

to historical convention, and industry standards, this is usually

sent in the form of GDSII Stream format

In

the old days 20-30 years ago, the final stream format layout of
the whole chip was put on magnetic tape, and hand carried to the fab
(aka the mask shop)

Hence the term tape out

There were sometimes problems getting a whole chip onto a single

magnetic tape

Now

tapeout is done across the network

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