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Outline
Coupling capacitance
CC (i, j ) f ij
Delay noise:
Lenij
Distij
CC
2
CC
2
b
critical sink
d ji Rsa CC Rab
non-critical sink
CC
2
Antenna effect
Diffusion
Sink 1
Sink 2
Diode insertion
Jumper insertion
Layer assignment
Reduce antenna length by layer
assignment. [ShirotaCICC98] [ChenISDFT00]
6
Antenna violation
Diffusion
Gate
Jumper insertion
Diffusion
Gate
Layer assignment
Diffusion
Gate
Given
Goal
Cr?
?
target wire i
other wire
10
Cr
k ,n ,1
k ,n , 2
CC ( k ,n 2 k ,n )
if k n / 2
otherwise
Derivation of k,n
a wire
potential slot
for empty tracks
k n / 2
12
Derivation of k,n,1
target wire i empty track
other wire
bundle
potential position
for empty tracks
k 1
k,n,1 not_on_boundary =2
1
k 1
(k 1)!
n k 1
k n / 2
k,n,1: total # of
permutations target wire
has one neighboring wire.
13
Derivation of k,n,1
target wireempty
i
track
other wire bundle
potential position
for empty tracks
k,n,1 on_boundary2 =
k n / 2
14
Derivation of k,n,2
target wire i
other wire
bundle
potential position
for empty tracks
k 1
k,n,2 = 2
2
k 1
(k 2)!
nk
k n / 2
16
Sink v
Antenna for
v
dont care region
for v
17
separators
18
An bottom-up approach,
adapted from
[KunduSIAM77], each node in
the tree processed at most
once.
At each node u, if W(Tu) >
Amax, remove minimum
number of separators in Tu
(assign to Ltop), such that the
resulting W(Tu) Amax.
A O(n) SPLIT technique to
find minimum separators.
W(Tu): total length of tree Tu
Amax=5
19
b
e
Amax=30
Amax,reduced=27
20
Amax=5
21
22
4.
5.
23
Layer 3
Layer 2
Layer 1
240ps230ps50ps
20ps100ps
Layer 0
24
Benchmark circuits
#GRC
#nets
#tracks
verti
panel
#tracks
hori panel
ibm01
6464
8.8K
10
10
ibm02
8064
15.7K
22
18
ibm03
8064
14.6K
15
14
ibm04
9664
17.9K
19
17
ibm05
12864
19.3K
34
32
ibm06
12864
21.9K
18
15
ibm07
19264
29.0K
23
21
ibm08
19264
36.3K
22
18
ibm09
25664
41.6K
18
14
ibm10
256128
43.7K
23
20
ibm11
256128
50.0K
13
12
ibm12
256128
51.6K
18
15
ibm13
256128
59.4K
13
12
25
Benchmark circuit
27
28
JI : Jumper
Insertion.
29
30
Conclusion
Thank you!
31
MF
(u )
W (b))
32
SPLIT example
33