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Technology Background
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Semiconductors and
Doping
Adding trace amounts
of certain materials to
N-Type
semiconductor has free electrons
dopant is (typically) phosphorus, arsenic, antimony
P-Type
semiconductor has free holes
dopant is (typically) boron, indium, gallium
Metal-oxide-semiconductor (MOS)
and related VLSI technology
pMOS
nMOS
CMOS
BiCMOS
GaAs
Fabrication Technology
Wafers
Fabrication Technology
Different parts of each die will be
made P-type or N-type (small amount
of other atoms intentionally
introduced - doping -implant)
Interconnections are made with
metal
Insulation used is typically SiO2. SiN
is also used. New materials being
investigated (low-k dielectrics)
Fabrication Technology
nMOS Fabrication
CMOS Fabrication
p-well process
n-well process
twin-tub process
Fabrication Technology
All the devices on the wafer are made at the same time
After the circuitry has been placed on the chip
the chip is overglassed (with a passivation layer) to protect it
only those areas which connect to the outside world will be left
uncovered (the pads)
CMOS Technology
BiCMOS
Complementary MOS
Inverter Layout
VDD
PMOS
In
Out
NMOS
Metal
Thick field oxide
p+
n+
n+
p substrate
p+
p+
n well
n+
Silicon IC processing
Similar to photographic printing
Expose the silicon wafer through a mask
Process the silicon wafer
Repeat sequentially to pattern all the layers
The wafer
Czochralski process
Melt silicon at 1425 C
Add impurities (dopants)
Spin and pull crystal
Wand
(a finished 250lb crystal)
A polished wafer
Fabrication Steps
Start with blank wafer (typically p-type where
NMOS is created)
First step will be to form the n-well (where
PMOS would reside)
Cover wafer with protective layer of SiO2 (oxide)
Remove oxide layer where n-well should be built
Implant or diffuse n dopants into exposed wafer to
form n-well
Strip off SiO2
p substrate
Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in
oxidation furnace
SiO 2
p substrate
Photoresist
Photo resist
Photoresist is a light-sensitive
organic polymer
Property changes where
exposed to light
Two types of photo resists
(positive or negative)
Positive resists can be removed
if exposed to UV light
Negative resists cannot be
removed if exposed to UV light
Photoresist
SiO 2
p substrate
Patterning
How we
pattern and
expose the
resist
To make the
patterns we
want on the
silicon
Lithography
Expose photoresist to Ultra-violate
(UV) light through the n-well mask
Strip off exposed photo resist with
chemicals
Photoresist
SiO 2
p substrate
Etch
Etch oxide with hydrofluoric acid (HF)
Only attacks oxide where resist has been
exposed
N-well pattern is transferred from the mask to
silicon-di-oxide surface; creates an opening to
the silicon surface
Photoresist
SiO 2
p substrate
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah
etch
p substrate
N-well
N-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic-rich gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2 shields (or masks) areas which remain p-type
SiO 2
n well
Strip Oxide
Strip off the remaining oxide using
HF
Subsequent steps involve similar
series of steps
n well
p substrate
Poly silicon
(self-aligned gate technology)
p substrate
n well
Self-Aligned Process
Use gate-oxide/poly silicon and
masking to expose where n+
dopants should be diffused or
implanted
N-diffusion forms nMOS source,
drain, and n-well contact
p substrate
n well
N-diffusion/implantation
Pattern oxide and form n+ regions
Self-aligned process where gate blocks ndopants
Polysilicon is better than metal for self-aligned
gates because it doesnt melt during later
processing
n+ Diffusion
p substrate
n well
N-diffusion/implantation cont.
Historically dopants were diffused
Usually high energy ionimplantation used today
But n+ regions are still called
diffusion
n+
n+
p substrate
n+
n well
P-Diffusion/implantation
Similar set of steps form p+
diffusion regions for PMOS source
and drain and substrate contact
p+ Diffusion
p+
n+
n+
p substrate
p+
p+
n well
n+
Contacts
Now we need to wire together the
devices
Cover chip with thick field oxide
(FO)
Etch oxide where contact cuts are
needed
Contact
n+
n+
p substrate
p+
p+
n well
n+
Metalization
Sputter on aluminum over whole wafer
Gold is used in newer technology
Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+
n+
n+
p substrate
p+
p+
n well
n+
CMOS INVERTER
VDD
V DD
V DD
Rp
PMOS
In
Out
NMOS
V out
V out
Rn
V in 5 V DD
V in 5 0
A Pentium cutaway
Figure courtesy
Yan Borodovsky,
Intel