215VLTO3-LOW POWER VLSI

CIRCUITS
UNIT-1 POWER DISSIPATION IN CMOS
OUTLINE
HIERARCHY OF LIMITS OF POWER
SOURCES OF POWER CONSUMPTION
PHYSICS OF POWER DISSIPATION IN CMOS FET DEVICES
BASIC PRINCIPLE OF LOW POWER DESIGN

WHY LOW POWER ?

Users need for:

Mobility
Portability
Reliability
Packaging costs
Power supply rail design
Chip and system cooling costs
Growth of battery-powered systems
Noise immunity and system reliability
Battery life (in portable systems)
Environmental concerns

LOW POWER DESIGN- Motivations

Minimize

power
Reduce power in various modes of device operation
Dynamic power, leakage power, or total power

Minimize

time
Reduce power quickly
Complete the design in as little time as possible
Prevent downstream issues caused by LPD techniques
Avoid complicating timing and functional verification

Minimize

effort
Reduce power efficiently
Complete the design with as few resources as possible
Prevent downstream issues caused by LPD techniques
Avoid complicating timing and functional verification

PRINCIPLES OF LOW-POWER DESIGN

Using the lowest possible supply voltage.

Using the smallest geometry, highest frequency devices but operating the
at the lowest possible frequency.

Using parallelism and pipelining to lower power required frequency of

operation

Power management by disconnecting the power source when the system is

idle.

Designing system to have lowest requirements on subsystem performance

for the given user level functionality.

MOORES LAW

Moore's Law was initially made in the form of an observation and forecast.

Main concepts :

Density of transistors double every two years.

Complexity of transistors for minimum cost double every year.
Two-Mil squares: Ability to build 500 transistors per linear inch or
250,000 per quarter inch.
Heat Dissipation: Direct access to heat generating sources.
High device yield: No fundamental obstacle to achieving device yield of
100%.

Moores Law Cont.

Moores Law - doubling transistors every 18 months.

Power is proportional to die area and frequency

In the same technology a new architecture has 2-3 Area

Changing technology implies 2X frequency

Increasing densities and clock frequencies pushed the reduce power supply.

HIERARCHY OF LIMITS OF POWER

PHYSICAL
DESIGN
CIRCUIT LEVEL

ARITHEMATIC
LEVEL

ALGORITHMIC LEVEL

SYSTEM LEVEL

HIERARCHY OF LIMITS OF POWER

Level

Particular tasks

System

Power down, System partitioning

Algorithm

Complexity, Locality, Concurrency,

Regularity,
Data representation

Architecture

Concurrency, Instruction set selection,

Signal correlation, Data representation

Circuit/Logic

Logic optimization, Novel circuits,

Transistor sizing, Voltage islands

Physical Design

Compact layout, Interconnects

Technology

SOI, Advanced packaging

Overview of Power consumption

Average power consumption

Dynamic power consumption
Short-circuit power consumption

Leakage power consumption

Static power consumption

Soures of power consumption

SOURCES OF POWER CONSUMPTION

Power Consumption Limits the number of transistors on a chip.
P=P

Switching

+P

Short-Circuit

+P

leakage.

PSwitching , called also switching power, is due to charging and discharging

capacitors circuit.

PShort-Circuit , called short-circuit power, is caused by the short circuit

currents that arise of PMOS/NMOS transistors are conducting

simultaneously.
PLeakage , originates from substrate injection and subthreshold effects. For
older techno m and above), PSwitching was predominant. For deepsubmicron processes, PLeakage becomes important.

Design for low-power implies the ability to reduce all three components

Transition Power

Gate output rising transition

Energy dissipated in pMOS transistor = CV 2/2
Energy stored in capacitor = CV 2/2
Gate output falling transition
Energy dissipated in nMOS transistor = CV 2/2
Energy dissipated per transition = CV 2/2
Power dissipation

Ptotal = Pdyn + Pstat

Ptran + Psc + Pstat
11

SOURCES OF ENERGY
CONSUMPTION

SOURCES OF POWER DISSIPATION

SYSTEM POWER
GATE POWER DISSIPATION
DYNAMIC
POWER

SWICTH
ING
POWER

STATIC POWER

SHORTCIRCUI
T

GLICTHIN
G POWER

LEAKAGE
POWER

PHYSICS OF POWER DISSIPATION IN CMOS FET DEVICES

Dynamic power dissipations: Whenever the logic level changes at

different points in the circuit because of the change in the input signals the
dynamic power dissipation occurs.
Switching power dissipation.
Short-circuit power dissipation.

Static power dissipations: This is a type of dissipation, which does not

have any effect of level change in the input and output.

Leakage power.

Low power design would look at the trade offs of the above issues.

SOURES OF POWER DISSIPATION

P = P switching +P short-circuit +P leakage +P static

POWER DISSIPATION

Physics of Power Dissipation in Devices

Physics of Power Dissipation in CMOS FET

Devices

CMOS GATE POWER EQUATIONS

Dynamic Power
Pdynamic CVDD 2 f

Dynamic power is required to charge and discharge load capacitances when

transistors switch.

One cycle involves a rising and falling output.

On rising output, charge Q = CVDD is required

On falling output, charge is dumped to GND

This repeats Tfsw times over an interval of T

VDD
iDD(t)

fsw

Dynamic Power Cont.

VDD
iDD(t)

fsw

Pdynamic CVDD 2 f
Pdynamic

DD

( t )VDD dt

VDD

DD

( t ) dt

VDD
Tf sw CVDD
T
CVDD 2 f sw

Lowering Dynamic Power

Capacitance:
Function of fan-out, wire length, transistor sizes

Supply Voltage:
Has been dropping with successive generations

Pdyn = CL VDD2 P01 f

Activity factor:

Clock frequency:

Lowering CL
Improves performance as well
Keep transistors minimum size (keeps intrinsic capacitance (gate and diffusion) small)
Transistors should be sized only when CL is dominated by extrinsic capacitance
(fanout and wires)
Reducing VDD has a quadratic effect
But has a negative effect on performance especially as VDD approaches 2VT
Reducing the switching activity, f01 = P01 * f
A function of signal statistics and clock rate
Impacted by logic and architecture design decisions

Switching Power Dissipation

P Swicthing =CV2 f

Caused by the charging and discharging of the node capacitance

CL is the output load of the gate, VDD is the supply voltage, fClock is the clock frequenc is
the switching activity of the gate, defined as the probability of the gates output to ma
transition during one clock cycle.

Figure 1: Switching power dissipation

Switching Power Dissipation

Switching Power Dissipation cont.

Reductions of PSwitching are achievable by:
supply voltage scaling
frequency scaling
minimization of switched capacitance
Ps/w=

0.5 * * CL* Vdd2 * fclk

CL physical capacitance, Vdd supply voltage, switching activity, fclk clock

frequency.
CL(i) = j CINj + Cwire + Cpar(i)
CIN the gate input capacitance, Cwire the parasitic interconnect and Cpar diffusion
capacitances of each gate.
Depends on:
Supply voltage
Physical Capacitance
Switching activity

Short - circuit power dissipation

Psc = fck Esc

When transistors switch, both nMOS and pMOS networks may be

momentarily ON at once

Leads to a blip of short circuit current.

< 10% of dynamic power if rise/fall times are comparable for input
and output

Short - circuit power dissipation

Increases with rise and fall times of input

Decreases for larger output load capacitance

Decreases and eventually becomes zero when VDD is scaled down but the
threshold voltages are not scaled down.

Escf =

tBtE VDD isc(t)dt

= (tE tB) Iscmaxf VDD / 2

Escf =

tf (VDD - |VTp| - VTn) Iscmaxf / 2

Escr =

tr (VDD - |VTp| - VTn) Iscmaxr / 2

Escf = Escr = 0, when VDD = |VTp| + VTn

Copyright Agrawal &
Srivaths, 2007

Low-Power Design and Test,

Lecture 2

26

Short Circuit Current, isc(t)

VDD
VDD - VTp

Vi (t)

Volt

n-transistor
cuts-off

Vo(t)

VTn

p-transistor0
starts
conducting

Iscmaxf

isc(t)

Isc
0

tB

tE
Copyright Agrawal &
Srivaths, 2007

Time (ns)

Low-Power Design and Test,

Lecture 2

27

Glitch Power Dissipation

Glitches are temporary changes in the value of the output unnecessary

transitions

They are caused due to the skew in the input signals to a gate

Glitch power dissipation accounts for 15% 20 % of the global power

Basic contributes of hazards to power dissipation are

Hazard generation
Hazard propagation

Glitch Power Dissipation

P = 1/2 .CL Vdd (Vdd Vmin) ;

Vmin : min voltage swing at the output

Glitch power dissipation is dependent on

Output load

Input pattern

Input slope

Hazard generation can be reduced by gate sizing and path

balancing techniques
Hazard propagation can be reduced by using less number of
inverters which tend to amplify and propagate glitches

Static Power
P

Istatic V

Static power is consumed even when chip is quiescent.

Ratioed circuits burn power in fight between ON transistors
Leakage draws power from nominally OFF devices
Vgs Vt
Vds
nvT
vT
ds
ds 0

I I e

1 e

Vt Vt 0 Vds s Vsb s

Leakage Power Dissipation

P=P

leakage

Leakage power as a fraction of the total power increases as clock frequency

drops. Turning supply off in unused parts can save power.
For a gate it is a small fraction of the total power; it can be significant for very
large circuits.
Scaling down features requires lowering the threshold voltage, which
increases leakage power; roughly doubles with each shrinking.

Multiple-threshold devices are used to reduce leakage power .

Isub= 0 Cox(W/L)Vt2 exp{(VGS VTH + VDS)/nVt}

VDS = drain to source voltage
: a proportionality factor

31

Leakage Power
VDD
Ground
Gate

IG

Source

Drain

n+

Isub

n+

IPT

Bulk Si (p)

IGIDL

nMOS Transistor

32

Leakage Current Components

Sub-threshold conduction, Isub

Reverse bias pn junction conduction, ID

Gate induced drain leakage, IGIDL due to tunneling at the gate-drain overlap

Drain source punch through, IPT due to short channel and high drain-source
voltage

Gate tunneling, IG through thin oxide; may become significant with scaling.

Sub-threshold Current

Isub = 0 Cox (W/L) Vt2 exp{(VGS VTH ) / nVt }

0: carrier surface mobility
Cox: gate oxide capacitance per unit area
L: channel length
W: gate width
Vt = kT/q: thermal voltage
n: a technology parameter
Copyright Agrawal &
Srivaths, 2007

Low-Power Design and Test,

Lecture 2

33

Increased Sub-threshold Leakage

Log (Drain current)

Scaled device

Ic

Isub
0 VTH VTH
Copyright Agrawal &
Srivaths, 2007

Gate voltage
Low-Power Design and Test,
Lecture 2

34

THANKYOU.