Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
TLK3101
TLK2701
TLK2501
TLK1501
TLK4250
TLK4120
TLK2521
TLK1521
TLK2201
TLK1201
TNETE2201
TLK2208
TLK2226
TLK2206
TLK1002
TLK4212
TLK3114SA
TLK3114SB
TLK3104SA
TLK3104SC
TLK3118
TXF100
TLK10021
SLK2721
SLK2701
SLK2511
SLK2501
SN65LVDS93
SN65LVDS94
SN65LVDS95
SN65LVDS96
SN65LV1023A
SN65LV1224A
SN65LV1021
SN65LV1212
Interface Home
In development
16-bit
LVTTL
P-S
8b/10b
Encoder
Clock
PLL
PRBS
Verification
16-bit
LVTTL
8b/10b
Decoder
Clock
Recovery
S-P
LOS
Back to
SerDes Summary
390 mW
390 mW
390 mW
360 mW
250 mW
TLK3101
2.5 3.125 Gbps
TLK2711
1.6 2.7 Gbps
TLK2711JR
1.6 2.7 Gbps
TLK2701
1.6 2.7 Gbps
TLK2501
1.6 2.5 Gbps
TLK1501
0.6 1.5 Gbps
In Production
*TLK2711 has VML driver with internal termination on Rx and TLK3101 has a VML driver with internal termination resistors
Back to
SerDes Summary
TLK2521
1.0 2.5 Gbps
< 540 mW
TLK1521
.5 1.24 Gbps
Lock indicator
Fast Synch mode
Equalization for long link lengths
Industrial temperature qualified
In Production
Back to
SerDes Summary
1 2.5 Gbps
TLK4120
19 mm
VML driver
Equalization for long link lengths
1.8 mm
Pitch: 1.0mm
Package height: 2mm (max)
Footprint: 368.6mm2 (max)
In Production
Samples Now
Back to
SerDes Summary
P-S
10-bits
or
5-bits (DDR)
Clock
PLL
PRBS
Verification
10-bits
or
5-bits (DDR)
Clock
Recovery
S-P and
Comma Detect
LOS
Back to
SerDes Summary
200 mW
200 mW
150 mW
600 mW
TLK2201Ajr
1.0 1.6 Gbps
TLK2201B
1.0 1.6 Gbps
TLK2201AI
I-temp 1.2 1.6 Gbps
TLK1201A
0.6 - 1.25 Gbps
TNETE2201B
1.25 Gbps
In Production
Note:
Single Channel Diagram
PRBS
TLK2208
10-bits
or
5-bits (DDR)
FIFO
P-S
8b/10b
Encoder
Clock
PLL
CTC
Clock
Recovery
PRBS
Verification
10-bits
or
5-bits (DDR)
8b/10b
Decoder
FIFO
S-P
< 1W
19 mm
1.8 mm
Pitch: 1.0mm
Package height: 2mm (max)
Footprint: 368.6mm2 (max)
In Production
Channel A, B (10-bits)
Channel C, D (10-bits)
TX
Channel E, F (10-bits)
MAC
ASIC
FPGA
Channel G, H (10-bits)
RX
Channel E, F (10-bits)
Channel A, B (10-bits)
TL
K2
20
8
Channel C, D (10-bits)
Channel G, H (10-bits)
TX
MAC
ASIC
FPGA
RX
Channel A (5-bits)
Channel B (5-bits)
Channel C (5-bits)
Channel D (5-bits)
Channel E (5-bits)
Channel F (5-bits)
Channel G (5-bits)
Channel H (5-bits)
Channel A (5-bits)
Channel B (5-bits)
Channel C (5-bits)
Channel D (5-bits)
Channel E (5-bits)
Channel F (5-bits)
Channel G (5-bits)
Channel H (5-bits)
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
TL
K2
20
8
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
Next
Back to
SerDes Summary
Power
TLK2206
< 1W
1- 1.3 Gbps
19 mm
1.8 mm
JTAG support
1.0 mm
Pitch: 1.0mm
Package height: 2mm (max)
Footprint: 368.6mm2 (max)
Samples Now
Back to
SerDes Summary
< 1W
19 mm
1.8 mm
RGMII Compliant
1.0 mm
Pitch: 1.0mm
Package height: 2mm (max)
Footprint: 368.6mm2 (max)
Samples 3Q04
Power
< 350 mw
< 350 mw
TLK4202
1.0 4.25 Gbps
Packaging
Package Type: 24 lead QFN
Pitch: .5mm
Package height: 1mm (max)
Footprint: 17.22mm2 (max)
Samples Now
Samples 4Q04
Back to
SerDes Summary
< 350 mw
Samples 3Q04
FIFO
P-S
8b/10b
Encoder
PLL
Clock
CTC
Only on TLK3114SA & TLK3124SA
PRBS
Verification
8/10-bit
SSTL/HSTL
8b/10b
Decoder
FIFO
Clock
Recovery
S-P
Back to
SerDes Summary
650mW/Ch
TLK3114SC
650mW/Ch
TLK3114SB
2.5 - 3.125 Gbps/Chv
650 mW/Ch
TLK3104SC
In Production
Next
TL
K
TLK3114SC
TL
K3
114
SA
310
4S
A
Note:
TLK3104SC has same features as TLK3104SA, but has 4 bit LVDS interface and 8/10b non-bypassable
Next
Switch
ASIC
TLK31x4
TLK31x4
10 Gigabit
TLK31x4
TLK31x4
10 Gigabit
TLK31x4
TLK31x4
TLK31x4
TLK31x4
Switch
ASIC
10 Gigabit
2.5 Gigabit
2.5 Gigabit
10 Gigabit
Back to
SerDes Summary
<425mW/Ch
TLK3118
3.2 Gbps/Ch
Samples Now
Next
XGMII
XGMII
XAUI
Back to
SerDes Summary
CDR
Photo DetectorTransimpedanc
e
Post
Amplifier
Amplifier
Clock Gen
Laser
Frame/
Map
Process
Laser Driver
Clock
Generation
Mux
Back to
SerDes Summary
Photo DetectorTransimpedanc
e
Amplifier
Post
Amplifier
SLK2501 Multi-Rate
transceiver and CDR
Frame/
Map
Process
E
O
Laser
Laser Driver
Frame/
Map
Process
Clock
Generation
Back to
SerDes Summary
Power
SLK2721
2.7Gbps/Ch
< 900 mW
SLK2701
< 900 mW
SLK2511
< 900 mW
SLK2501
2.7Gbps/Ch
2.5 Gbps/Ch
2.5 Gbps/Ch
In Production
(worse case)
Device Differences
SLK2721: SLK2701 with improved receiver tolerance
SLK2701: Multi-rate / OC-48 FEC Data rate up to 2.7
Back to
Gbps
SerDes Summary
SLK2511: SLK2501 with clock input 155MHz &
622MHz
Samples 2Q04
Back to
SerDes Summary
Traffic or
Queue
Manager
Packet or
Network
Processor
XFP Module
MAC or
ASIC
XFI-XAUI
Bridge
XAUI
3Gbps
XFI
10Gbps
CDR
TOSA
ROSA
Optics
System
Back to
SerDes Summary
SN65LVDS95/96
1.3 Gbps throughput
SN65LVDS93/94
1.8 Gbps throughput
In Production
DATA
(LVDS)
PARALLEL
TO
SERIAL
PARALLEL
TO
SERIAL
140 455Mbps
SERIAL
TO
PARALLEL
140 455Mbps
SERIAL
TO
PARALLEL
Interface
28-bit
or
21-bit
CLK
PARALLEL
TO
SERIAL
140 455Mbps
SERIAL
TO
PARALLEL
PARALLEL
TO
SERIAL
140 455Mbps
SERIAL
TO
PARALLEL
PHASE
LOCKED
LOOP
20 65MHz
PHASE
LOCKED
LOOP
CLOCK
(LVDS)
Interface
28-bit
or
21-bit
CLK
Back to
SerDes Summary
SN65LV1023A
100-660 Mbps transmitter
SN65LV1224A
100-660 Mbps receiver
SN65LV1021
100-400 Mbps transmitter
SN65LV1212
100-400 Mbps receiver
In
Production
Next
SN65LVDS1212/1224
SN65LV1212/1224A
A-
Y+
Y-
Output Latch
TCLKR/F
A+
LVDS
Serial-to-Parallel
DIN(LVTTL)
Input Latch
10
Parallel-to-Serial
LVDS
10
DOUT (LVTTL)
TCLK
PLL
Timing /
Control
SYNC1
SYNC2
DEN
PLL
Timing /
Control
Clock
Recovery
Note:
(1021/1212) TCLK = 10MHz 40MHz then LVDS serial line speed = 360-792 Mbps line speed*
(1023A/1224A) TCLK = 10MHz 66MHz then LVDS serial line speed = 120-480 Mbps line speed*
* 20% overhead [10 data + 2 clock bits]
REFCLK
REN
LOCK
RCLKR/F
RCLK
Back to
SerDes Summary
SLK2501/SLK2511/SLK2701/SLK2721
SONET OC-3 to OC-48 Txcvr with Mux, De-Mux, CDR and Clock
Line Module
Photodiode
Laser
Diode
Reference
clock
TIA
Clock
Buffer
Memory
PA
LD
PLL Multiplier
Front
Plane
Serdes
MAC
Framer/
Mapper
NPU/
ASICs
Back
Plane
Serdes
Clock
Buffer
Back to
SerDes Summary