2.

44 GHZ LOW
NOISE AMPLIFIER
DESIGN
(LNA)
YASYA VALLABHANENI
DHARIT SURA

RFIC BLOCK

Amplify very weak signals (eg:captured by Antenna)

Key component placed at the front end of the radio receiver circuit
Noise from the subsequent receiver chain is reduced by the gain of LNA

NF frontend NFLNA

NFsubsequent 1
GLNA

APPLICATIONS: Used in various applications like ISM Radio, Cellular/PCS

Handsets, GPS Receivers, Cordless Phones, Wireless LANs, Wireless Data,

OBJECTIVE OF DESIGN

Operate over 2.44 Ghz (Wifi

Applications)

Achieve a good noise performance

Have a good linearity performance

Consume minimum power

LNA DESIGN CONSIDERATIONS

Noise performance
Power transfer
Impedance matching
Power consumption
Bandwidth
Stability
Linearity

REQUIRED SPECIFICATIONS OF OUR DESIGN

OBJECTIVE: To design an Inductor Source Degenerated LNA to meet
the specifications outlined for IEEE802.11
PARAMETER

SPECIFICATIONS

UNITS

Frequency

2.44

Ghz

Noise Figure

<2.5

dB

Gain

>10

dB

S11

<-20

dB

S22

<-10

dB

IP3

>-5

dB

50

Ohms

Source/Load Impedance

Technology Parameters: =0.9, =2.2,=4.4, tox=1.4xm,

=0.433/V.s, Vth0=0.7086V,=3.9x(8.85x)F/m

BASIC SCHEMATIC OF LNA

Lg

COMPONENT DESCRIPTION
=Set the resonance frequency to 2.44Ghz
=Matches input impedance
=Tuned output increases gain and works as Band Pass Filter with
=Source Impedance
M=Nmos transistor with 0.6um technology

DESIGN EQUATIONS
Input Impedance Matching equations
Zin=Rs

Z in s ( Lg Ls )

02

1
( Lg Ls )C gs

g m Ls
Rs
C gs

C gs

1
g L
m s
sC gs
C gs

2
CoxWL
3

NF

Effective Transconductance

Geff

I out g m ( sC gs )

Vs
Rs Z in

gm
1 s ( RsC gs g m Ls ) s 2C gs ( Lg Ls )

Noise Figure
N
G N in
4kT g m
device
1
g m2
G N in
4kTRs 2
( RsCgs g m Ls ) 2

2 ( RsCgs g m Ls ) 2
Rs g m
NF 1
0

4 Ls
L g Ls

Contd.
Inductor design equations

Quality Factor

Ls Rs T

Power transfer in degenerate circuit

S11

1 s 2C gs ( Lg Ls ) sg m Ls sRs C gs
Z in Z s*

Z in Z s
1 s 2C gs ( Lg Ls ) sg m Ls sRs C gs
1 s 2C gs ( Lg Ls )

1 s ( g m Ls Rs C gs ) s 2C gs ( Lg Ls )

S 21 2Geff RL

1 s ( Rs C gs

2 g m RL
g m Ls ) s 2C gs ( Lg Ls )

Contd
Power Consumption

P I DVDD
P

L2

Rs2

02

Cox W
2

(Vgs VT ) 2 VDD

1
L3s (1 Lg / Ls )

Stability Factor

1 | S22 |2 | S11 |2 | S |2
K
1
2 | S12 S21 |
3rd Order Intercept Point

DISADVANTAGES OF BASIC SCHEMATIC

Low stability
Low gain
Self biasing transistor has worse input reflection
(S11)
Sensitive to process variation and component
tolerance

CURRENT MIRROR CIRCUIT TO INCREASE

GAIN
Advantages of using
current mirror
The use of current
mirrors in biasing can
result in superior
insensitivity of circuit
performance to
variations in power
supply and
temperature
Used as a load
element in transistor
amplifiers, the high
incremental resistance
of the current mirror
results in high voltage
gain at low power

SIMULATION RESULTS(NF,KT AND GT)

DESIGN OF CASCADE STAGE

Initial Circuit
Diagram

SMALL SIGNAL ANALYSIS AND BW

ESTIMATION
Using open circuit time constant method we found the bandwidth of the circuit
from the small signal equivalent model

BW=(1/Tau)~1.12Ghz

CALCULATION V/S SIMULATED

Parameters

Calculation

Simulation

479um

400.05um

479um

575um

6.689nH

6.45nH

937pF

985pF

50ohms

175ohms

(1:20)

(1:50)

4.4nH

4.25nH

SCHEMATIC VIEW IN CADENCE

SIMULATION RESULTS
AC Response

w1

w2

BANDWIDTH=w2-w1=90Mhz

S11(Input Reflection Coefficient)

S22(Output Reflection Coefficient)

Nf(Noise Figure)

Kf(Stability)

GT(Transducer Gain)

GP(Gain Power)

GA(Gain Available)

IP3(3rd Order Intercept Point)

ADVANTAGES

High Stability
High Gain
Consumes minimum Power
Good linearity performance

RESULTS
Parameters

Target

Simulated

Frequency

2.45Ghz

2.44Ghz

Noise Figure

<2.5dB

935.6mdB

Gain

>10dB

14.68dB

S11

<-20dB

-20.28dB

S22

<-10dB

-14.95dB

IP3

>-5dB

-3.6dB

FUTURE WORK

We can reduce the applied Voltage

Thereby reducing the power consumption
further
Increase Gain
Use short channel Mosfets
Layout Design and compare the schematic
parameters