Inputs

Outputs

Combinational
circuit
Next
state

Memory
elements

Present
state

Clock
a periodic external event (input)

Clock

Comparision b/w combinational &

sequential logic circuits.
combinational

sequential

The output variables are at all

times dependent on the
combination of input
variables

The output variables

dependent not only on present
input variables but also
depend upon the past
information

Memory unit is not required

Memory unit is required to

store the past information

Faster in speed , because the

delay b/w input & output is
due to propagation delay of
logic gates

Slower than the combinational

circuits

These are easy to design

These circuits are

comparatively harder to
design

It does not have a clock signal

It may or may not have a clock

signal . Most sequential
circuits have a clock signal

Classification of sequential logic circuits

(depending on timing of their signals)
Synchronous

Asynchronous

The change in input signal

can effect memory
element upon activation
of clock signal

The change in input signal

can effect memory
element at any instant of
time.

Memory elements are

clocked flip-flops

Memory elements are

either unclocked flip-flops
or time delay elements

The maximum operating

Because of absence of
speed of clock depends on clock asynchronous
time delays involved
circuits operate faster
than synchronous circuits
Easier to design

More difficult to design

Memory elements are either latches or flip-flops.

The main difference b/w latches & flip-flops is in

the method used for changing their state.

Flip-flop is a logic circuit used to store one bit of

binary information.
Latch is an unclocked flip-flop.

Types:
SR
D
JK
T

S-R Latch with NORs

R (reset)

Q
S (set)

S R

Q Q

1
1
0
0

0
1
0
0
1

1
0
1
0

0
0
1
1
0

S-R latch made from cross-coupled NORs

If Q = 1, set state
If Q = 0, reset state
Usually S=0 and R=0
S=1 and R=1 generates unpredictable results

Undefined
Set
Reset
Stable

SR Latch Analysis
Consider the four possible cases:

a) S = 1, R = 0
b) S = 0, R = 1
c) S = 0, R = 0
d) S = 1, R = 1

SR Latch Analysis
a) S = 1, R = 0: then Q = 1 and Q
=0

00

b) S = 0, R = 1: then Q = 0 and Q
=1

01
1

N1

N2

1
1

N1

11

0 0

00

00
0

N2

11

SR Latch Analysis
We got Memory!

c) S = 0, R = 0: then Q = Qprev and Q =

QQprev = 0

Qprev = 1

prev

11
00
S

N1

N2

00

11

00

11

N1

11
Q

00

N2

d) S = 1, R = 1:
then Q = 0 and Q = Invalid state: Q NOT
0
Q
R

00

00
1

N1

N2

00

TRUTH TABLE
INPUTS

Prese
nt
state

Next state

Qn

Qn+1

Qn+1

0
1
1

1
0
1

STATE

NO
CHANGE

RESET

SET
INDETER
MINATE

S-R Latch with NANDs(ACTIVE LOW):

S

S R Q

0
0
1
1

1
0
1
1
0

0
1
0
1

1
1
0
0
1

Disallowed
Set
Reset
Store

Latch made from cross-coupled NANDs

Sometimes called S-R latch
Usually S=1 and R=1
S=0 and R=0 generates unpredictable results

A) S=0, R=1
SET

B) S=1, R=0
RESET

C) S=1, R=1 (NO

CHANGE)

D) S=0, R=0
(PROHIBITED)

inputs

Present
state

Next state

Qn

Qn+1

Qn+1

STATE

INDETER
MINATE

0
1
1

1
0
1

SET

RESET
NO
CHANGE

S-R Latches

S-R Latch with NANDs(ACTIVE HIGH):

STATE

NO
CHANGE

RESET

SET

INDETER
MINATE

S-R Latch with control input

B) S=0, R=1
(RESET)

C) S=1, R=0
(SET)

D) S=1, R=1
(PROHIBITED)

Triggering in flipflops
Level triggering (in latches)
Positive level triggering
Negative level triggering

Flipflops:
Pulse triggering (+ve & -ve)
Edge triggering (+ve & -ve)

Hi-Lo edge

Lo-Hi edge

Abstract Representations
D

CK

CK

D-Latch
(Positive Level Triggered)

CK

D-Latch
(Negative Level Triggered)

D-Flip Flop
(Rising Edge Triggered)

CK

D-Flip Flop
(Falling Edge Triggered)

Clocked SR Flip-Flop

TRUTH TABLE
CLOCK
(enable
)

Qn

Qn+1

STATE

Qn

no
change

no
change

1
1

1
1

1
1
1

RESET

SET
INDETE
RMINAT
E

SR Flip Flop Waveform Diagrams :

To draw waveforms for flip flops you need to begin with an initial condition at Q, mark the
area where the clock input is asserted and then draw the output response. Lets use an
initial condition of Q =0.
The initial condition Q =0 is
marked as a dot on the output
waveform diagram.

Set

The flip flop has a negative edge

triggered clock. The clock is
asserted when Clk makes a
transition from 1 to 0. The
asserted zone is marked off in
yellow.

Reset

Analyze the waveform and draw

Q.

Clock

>Clk
R

Until
On
Onthe
this
thisclock
negative
negative
changes
edge
edgefrom
S=R=0:
S=11and
to No
0R=0:
it Change
is NOT
SET asserted.
Mode.
Mode.
Q
holds
Thus
ThusQQsets
holds
to at
1. Thus
0.
NoNo
analysis
analysis
is at
required
is 0.
required
until
until
thenext
next
negative
negative edge.
edge.

CHARACTERISTIC TABLE

SR

Qn+1

Qn

00

01

11

10

Q( t )

Characteristic Equation:

Q+ = S + R Q

EXCITATION/APPLICATION TABLE
Qn

Qn+1

D-Latch
C

0
1
1

x
0
1

No change
0
1

Advantages over S-R Latch

Single input to store 1 or 0
Avoid spurious input of S=1 and R=1

D Latch Timing Diagram

clock

clock enables input to be seen

output follows input in here

Clocked D Flip-Flop
Stores a value on the positive edge of C
Input changes at other times have no effect on output

Clocked D Flip-Flop
D

CP
5

TRUTH TABLE
CLOCK
(enabl
e)

1
1

1
D

Qn

Qn+1 STATE

Qn

EXCITATION/APPLICATION
TABLE

Q+ = D

no
chang
e
RESET

Qn

Qn+1

CHARACTERISTIC TABLE

SET

Qn+1

Clocked J-K Flip Flop

TRUTH TABLE
CLOCK

Qn

Qn+
1

Qn+
1

STATE

Qn

Qn

no
change

no
change

1
1

1
1

1
1
1

RESET

SET
TOGGL
E STATE

CHARACTERISTIC TABLE

JK

Q
0

00

01

11

10

K
Q+ = D = JQ + KQ

Qn+1

Qn

Qn

EXCITATION/APPLICATION TABLE

Qn

Qn+1

Clocked J-K Flip Flop

Two data inputs, J and K
J -> set, K -> reset, if J=K=1 then toggle output

Characteristic Table

J-K Latch: Race Condition

Set

Reset

100

Toggle

J
K
Q
\Q

Toggle Correctness: Single State change per clocking event

Solution: Master/Slave Flipflop

TRUTH TABLE
CLOC
K

Qn

Qm

Qs

0
0
1
1
0
0
1
1

NC

NC

NC

NC

NC

NC

NC

NC

CLOC
K

Qn

Qm

Qs

0
0
1
1
0
0
1
1

NC

NC

NC

NC

NC

NC

NC

NC

Timing diagram for master-slave JK

FLIPFLOP

Timing diagram for master-slave JK

LATCH

Timing diagram for a master-slave

SR flip-flop

Timing diagram for a master-slave

SR LATCH

Clocked T- Flip Flop

Toggle Flip-Flops
T

clk

T
Q

TRUTH TABLE
CLOC
K

Qn

Qn+1

Qn+1

STATE

Qn

Qn

no
chang
e

no
chang
e

1
1
0
CHARACTERISTIC
TABLE
1
1

Qn+1

Qn

Qn

Q(t+1) = TQ(t) + TQ(t)

= T Q(t)

TOGGL
E
0EXCITATION/APPLICATION
1
TABLE
Qn

Qn+1

Asynchronous Inputs
J, K are synchronous inputs
o Effects on the output are synchronized with the CLK input.
Asynchronous inputs operate independently of the
synchronous inputs and clock
o Set the FF to 1/0 states at any time.

Asynchronous Inputs

Master-Slave Edge-Triggered Flip-Flop

Can connect two level-sensitive latches in MasterSlave configuration to form edge-triggered flip-flop
Master latch catches value of D at QM when
CLK is low
Slave latch causes Q toQchange only at rising edge
D
Q
of CLK
Master
Slave
M

Latch
CLK
CLK
CLK
D
QM
Q

Latch
2 x 8 = 16 Transistors

Alternative Edge-Triggered
Flip-Flop
VDD

CLK

VDD

CLK

CLK

Q
CLK

CLK

GND
D

24 Transistors

8 Transistors

GND

Flip-flop timings
1)Setup time: It is the minimum time for which the
control levels need to be maintained constant on
the input terminals of the flip-flop, prior to the
arrival of the triggering edge of the clock pulse, in
order to enable the flip-flop to respond reliably.
2)Hold time: It is the minimum time for which the
control levels need to be maintained constant on
the input terminals of the flip-flop, after the
arrival of the triggering edge of the clock pulse, in
order to enable the flip-flop to respond reliably.
3)Propagation Delay: It is the time interval between
the time of application of the triggering edge or
asynchronous inputs and the time at which the
output actually makes a transition.
tPLH : It is measured from the triggering edge of
clock pulse (or preset input) to the LOW to HIGH

Setup and Hold Times

D

Q
Clk

setup
time

Setup Time: How long a signal must be stable

preceding the clock edge
Hold Time: How long a signal must be stable after the
clock edge

hold
time

Clk

Setup: Pass
Hold: Pass

Setup: Fail
Hold: Pass

Setup: Pass
Hold: Fail

Setup: Fail
Hold: Fail

Setup and Hold times: Flip Flops

20ns

5ns

20ns

5ns

74LS74 Positive
Edge Triggered
D Flipflop
Clk

Q
23/13ns
Setup time 20ns
Hold time 5ns
Propagation delays
- Low to High 23 ns max, 13 ns typ
- High to Low 40 ns max, 25 ns typ

40/25ns

Propagation Delays in an SR
Latch

Propagation delay the time it takes a

change in an input signal to produce a
change in an output

CONVERSION OF FLIPFLOPS
1)SR FLIPFLOP TO D-FLIPFLOP:
INPUT(D
)

PRESENT
STATE(Qn
)

NEXT
STATE(Qn+
1)

FLIP FLOP
INPUTS
S
R

1
S=D
R=D

2)SR-FLIPFLOP TO JK-FLIPFLOP:
J

Qn

Qn+1

Q
Q
clk

Q
Q

R = K + Qn
S = J + Qn

3)D flipflop to JK Flip-Flop

Qn

Qn+1

0
1
1

1
0
1

D = K Qn + J Qn

D flipflop to JK Flip-Flop

K
CLK

D
Latch

Q
Q

4)Toggle Flip-Flop from D-flipflop

Toggles stored value if T = 1 when

CLK is high
Q
D
Latch

T
CLK

Qn

Qn+1

D = T Q(t)