Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Chapter 10
Input/Output and Stable
Storage
Copyright 2008 Umakishore Ramachandran and William D. Leahy Jr.
Device Controller
Input/Output
Device
Address
Data
Main memory
Data register
(address = 5000)
7
Ready
0
IF
IE
Status register
(address = 5002)
Keyboard controller
10.3 DMA
CPU
Memory bus
DMA controller
Status
Go
Command
Memory
Device address
Count
256 bytes
Buffer
10.4 Buses
System Bus (or Memory Bus) is key
resource in entire design.
Functionally, bus has following
components:
Address lines
Data lines
Command lines
Interrupt lines
Interrupt acknowledge lines
Bus arbitration lines
10.4 Buses
CPU
System bus
Bridge
Memory
PCI bus
Controller
Controller
Controller
I/O processor
System bus
Bridge
I/O bus
Shared
Memory
Controller
Controller
Controller
10.6.1 An
Example
Command
pan()
tilt()
zoom(z)
Start
Stop
memory
buffer(M)
number of
frames (N)
Controller Action
Pan the camera view by
Tilt camera position by
Zoom camera focus by z
Start camera
Stop camera
Set memory buffer address for data
transfer to M
Set number of frames to be captured
and transferred to memory to N
10.6.1 An Example
//
//
//
//
//
//
//
10.6.1 An Example
// Start DMA transfer
camera_start_data_transfer() {
start_camera();
start_DMA();
}
// Stop DMA transfer
camera_stop_data_transfer() {
// automatically aborts data transfer
// if camera is stopped;
stop_camera();
}
// Enable interrupts from the device
camera_enable_interrupt() {
enable_interrupt();
}
// Disable interrupts from the device
camera_disable_interrupt() {
disable_interrupt();
}
10.6.1 An Example
// Device interrupt handler
camera_interrupt_handler() {
// This will be coded similar to any
// interrupt handler we have seen in
// chapter 4.
//
// The upshot of interrupt handling may
// to deliver events to the upper layers
// of the system software (see Figure 10.9)
// which may be one of the following:
// - normal I/O request completion
// - device errors for the I/O request
//
}
Input/output
Human in
the loop
Yes
PIO
DMA
Keyboard
Input
Mouse
Input
Yes
80-200 bytes/sec
Graphics display
Output
No
200-350 MB/sec
Input/Output
No
100-200 MB/sec
Network (LAN)
Input/Output
No
1 Gbit/sec
Modem
Input/Output
No
1-8 Mbit/sec
Output
Output
No
No
20-40 KB/sec
200-400 KB/sec
Voice
(microphone/speaker)
Audio (music)
Input/Output
Yes
10 bytes/sec
Output
No
4-500 KB/sec
Flash memory
Input/Output
No
10-50 MB/sec
CD-RW
Input/Output
No
10-20 MB/sec
DVD-R
Input
No
10-20 MB/sec
Inkjet printer
Laser printer
X
X
X
X
Head
Track
Spindle
Sector
Arm
Head
Assembly
All heads move
together
Platter
Cylinder X: Track X
from all 12 surfaces
(2 per platter)
Notation
Units
Throughput
n/T
Jobs/sec System-centric
metric quantifying
the number of I/O
requests n
executed in time
interval T
Avg.
Turnaround
time (tavg)
(t1+t2++tn)/n
Seconds System-centric
metric quantifying
the average time it
takes for a job to
complete
Avg. Waiting
time (wavg)
((t1-e1) + (t2-e2)+ +
(tn-en))/n
or
(w1+w2+ +wn)/n
Seconds System-centric
metric quantifying
the average waiting
time that an I/O
request experiences
ti
Response
time/
turnaround
time
Description
Name
Notation
Variance in
E[(ti tavg)2]
Response time
Units
Description
Seconds User-centric metric
2
that quantifies the
statistical variance
of the actual
response time (ti)
experienced by an
I/O request i from
the expected value
(tavg)
Variance in
Wait time
E[(wi wavg)2]
Starvation
Assumptions for
Disk Scheduling Algorithms
Disk has 200 tracks numbered 0 to
199
(with 0 being outermost and 199 being
innermost).
t3
t1
head
t4
t2
t3
t1
head
t4
t2
head t3
Innermost
track
t4
t1
t6
t5
t2
head t3
t4
t1
Retract
t6
t5
t2
Response time
FCFS
SSFT
R1 (cyl 20)
R2 (cyl 17)
R3 (cyl 55)
R4 (cyl 35)
R5 (cyl 25)
R6 (cyl 78)
R7 (cyl 99)
Average
3
6
44
64
74
127
148
66.4
7
10
48
28
2
71
92
36
LOOK
155
158
32
12
2
55
76
70
Firewire (Apple)
100 Mb/s
Why serial?
Smaller
Cheaper
No cross-talk
Serial signaling can be operated faster than parallel (Higher frequencies)
10.12 Summary
Mechanisms for communication
between processor and I/O devices
including programmed I/O and DMA.
Device controllers and device drivers.
Buses in general and evolution of I/O
buses in particular, found in modern
computer systems.
Disk storage and disk-scheduling
algorithms.