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Intel 8086
8086
MICROPROCESSOR
MICROPROCESSOR
1
Features
It is a 16-bit p.
8086 has a 20 bit address bus can access
up to 220 memory locations (1 MB).
It can support up to 64K I/O ports.
It provides 8, 16 -bit registers.
Word size is 16 bits.
It has multiplexed address and data bus
AD0- AD15 and A16 A19.
It requires single phase clock with 33% duty
cycle to provide internal timing.
2
Intel
Intel 8086
8086 Internal
Internal Architecture
Architecture
10
11
EXECUTION UNIT
Decodes instructions fetched by the BIU
Generate control signals,
Executes instructions.
The main parts are:
Control Circuitry
Instruction decoder
ALU
12
EXECUTION
EXECUTION UNIT
UNIT General
General Purpose
Purpose Registers
Registers
16 bits
AX
BX
CX
DX
8 bits
8 bits
AH
AL
BH
BL
Base
CH
CL
Count
DH
DL
SP
Pointer
BP
SI
Index
DI
Accumulator
Data
Stack Pointer
Base Pointer
Source Index
Destination Index
13
Register
Purpose
AX
AL
AH
BX
CX
CL
DX
Over flow
O
F
Direction
U - Unused
D
F
IF
TF SF ZF U
Interrupt Trap
Sign
A
F
PF U
Auxiliary
Zero
Parity
17
CF
Carry
Parity (PF)
Purpose
Holds the carry after addition or the borrow after subtraction.
Also indicates some error conditions, as dictated by some
programs and procedures .
PF=0;odd parity, PF=1;even parity.
Auxiliary (AF) Holds the carry (half carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result
(for example, in BCD addition or subtraction.)
Zero (ZF)
Shows the result of the arithmetic or logic operation.
Z=1; result is zero. Z=0; The result is 0
Sign (SF)
Flag
Purpose
Trap (TF)
A control flag.
Enables the trapping through an on-chip debugging
feature.
Interrupt (IF)
A control flag.
Controls the operation of the INTR (interrupt request)
I=0; INTR pin disabled. I=1; INTR pin enabled.
Direction (DF)
A control flag.
It selects either the increment or decrement mode for DI
and /or SI registers during the string instructions.
Overflow (OF)
Segmented Memory
The memory in an 8086/88
based system is organized as
segmented memory.
Physical Memory
00000
FFFFF
23
1 MB
Segment registers
In 8086/88 the processors have 4 segments
registers
Code Segment register (CS), Data Segment
register (DS), Extra Segment register (ES) and
Stack Segment (SS) register.
All are 16 bit registers.
Each of the Segment registers store the upper 16
bit address of the starting address of the
corresponding segments.
26
27
MEMORY
00000
BIU
34BA0
Segment Registers
CSR
ESR
SSR
44EB
54EB
44EB0
54EAF
54EB0
DATA (64K)
EXTRA (64K)
64EAF
695E
695E0
STACK (64K)
795DF
28
1
MB
DSR
44B9F
34BA
CODE (64k)
30
34BA
IP
8AB4
Code segment
34BA0
8AB4 (offset)
3D645
34BA0(CS)+
8AB4(IP)
3 D 6 5 4 (next address)
44B9F
31
Required Address
0001
0000
BIU
AX
AH
AL
BX
BH
BL
CX
CH
CL
DX
DH
DL
SP
BP
SI
IP
D
E
C
O
D
E
R
Fetch &
store code
bytes in
C
O PIPELINE C
D PIPELINE
(or)
E
O QUEUE
U
T
O
D
E
I
N
CS
DS
ES
SS
IP
BX
DI
DI
SP
BP
SI
DI
FLAGS
ALU
Timing
control
Default Assignment
34