Mustafa Khairallah

Boost Valley

Boost Valley Consulting

Universal Verification
Methodology (UVM)
Benefits

Verification Needs
UVM Benefits
Example: I2S
Conclusion

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Outline

Code
Reuse

Test
Functiona
Cases &
l
Scenarios Coverage
Modificati Calculatio
on
n

Generatin
g&
Debuggin Communica
tion
Managing
g
Reports

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Verification Needs

Code
Reuse

Test
Functiona
Cases &
l
Scenarios Coverage
Modificati Calculatio
on
n

Generatin
g&
Debuggin Communica
tion
Managing
g
Reports

Boost Valley Consulting

Verification Needs - Development

Code
Reuse

Test
Functiona
Cases &
l
Scenarios Coverage
Modificati Calculatio
on
n

Generatin
g&
Debuggin Communica
tion
Managing
g
Reports

Boost Valley Consulting

Verification Needs - Compilation

Code
Reuse

Test
Functiona
Cases &
l
Scenarios Coverage
Modificati Calculatio
on
n

Generatin
g&
Debuggin Communica
tion
Managing
g
Reports

Boost Valley Consulting

Verification Needs - Runtime

Code
Reuse

Test
Functiona
Cases &
l
Scenarios Coverage
Modificati Calculatio
on
n

Generatin
g&
Debuggin Communica
tion
Managing
g
Reports

Boost Valley Consulting

Verification Needs - Debugging

Verification Methodologies
Do the same things the same way:

Test/Test-bench separation:
Compile once, run many times.

Utilities:
Functional coverage reporting
mechanisms - etc.

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Ease of communication.

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UVM Benefits
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UVM Adoption

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Test/Test-bench separation
Test

Analysis
Agent
Configuratio
ns

Passive
Agent

Active
Agent
Bus
Agent

Register
Model

Environme
nt

Tes
t
En
v
(Test(Testbench)
bench)

DUT

UVC
s

Selects
Selects sequences,
sequences,
Configures
Configures the
the
environment(s)
environment(s)
Runs
Runs test.
test.

UVC
UVC User:
User: Integrates
Integrates
UVCs
UVCs into
into
environment
environment to
to test
test
different
different designs.
designs.

Developer:
Developer: UVC
UVC
Design
Design
Complication
Complication phase.
phase.

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Environment

Test
Test Writer:
Writer:

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Test/Test-bench separation

Environment

Analysis
Agent
Configuratio
ns

Passive
Agent

Active
Agent
Bus
Agent

Register
Model

Environme
nt

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Test

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Configurability

Configurations can be:

Structural configurations.
Runtime configurations.

Provides topological flexibility:

Components can be overridden,
removed or configured.

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Controlled by the test writer.

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 UVM is compatible with the TLM 2.0 standard.

Uses port/export communication.
Hides communication details (pin level activities)
Eases customization using configurations &
overrides.

Block 1

Block
Block 2
2

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TLM 2.0

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Constrained
Randomization

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Coverage Collector

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Checker (Reference
Model)

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Checker (Assertions)

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Built-in reporting
mechanisms.

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Built-in reporting
mechanisms.

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Practical Example
2
:I S

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Introduction

I2S Bus Purpose:

Communicate PCM audio data between integrated
circuits.

Characteristics
Separates clock and serial data signals.
Lower Jitter.
Can recover clock from data stream.

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I2S stands for Inter-IC Sound,

DUT is a slave I2S transceiver.
It is around 2000 gates.

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UVM Test-Bench
Architecture

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> 10
Runtime Comparison

Times
Reduction
!!

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Time in
14
minute
s
VHDL

UVM

10

VHDL Test-Bench

UVM Test-Bench
6

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No. of test cases

0
2

20

200

2000

20000

200000

2000000

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Summary

Mainly simulationbased
Limited assertionbased capabilities

Mostly directed testing

UVM Test-Bench
Simulation based
Advanced assertionbased in System
Verilog & UVM
Constrained random
testing & directed
testing

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Conventional Testbench

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Conventional Testbench

UVM Test-Bench

Cant automatically
guarantee full functional
coverage

Supports functional
coverage

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Summary

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Conventional Testbench

UVM Test-Bench

Strongly coupled with

DUT

Loosely coupled with

DUT

Requires longer
development time

Reusability reduces
development time

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Summary

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Questions?
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Thank You

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