SRM UNIVERSITY

FACULTY OF ENGG. & TECH.

DEPARTMENT OF CSE
B.Tech CSE Sem. 3
CS1003 DIGITAL COMPUTER FUNDAMENTALS
(Regulations 2013)

Prepared by,
M. Eliazer
Asst. Prof.(Sr.G)/CSE

Unit-4
Sequential Logic Circuits
Latches and Flipflops
Triggered flip flops
Clocked flipflops
State reduction and assignment
Counters
Registers
2

Sequential Circuits
Every digital system is likely to have combinational
circuits, most systems encountered in practice also
include storage elements, which require that the
system be described in term of sequential logic.

Synchronous Clocked
Sequential Circuit
A sequential circuit may use many flip-flops to store
as many bits as necessary. The outputs can come
either from the combinational circuit or from the flipflops or both.

Latches

SR Latch

The SR latch is a circuit with two cross-coupled NOR

gates or two cross-coupled NAND gates. It has two
inputs labeled S for set and R for reset.

SR Latch with NAND Gates

SR Latch with Control

Input
The operation of the basic SR latch can be modified
by providing an additional control input that
determines when the state of the latch can be
changed. In Fig. 5-5, it consists of the basic SR latch
and two additional NAND gates.

D Latch
One way to eliminate the undesirable condition of
the indeterminate state in SR latch is to ensure that
inputs S and R are never equal to 1 at the same time
in Fig 5-5. This is done in the D latch.

Graphic Symbols for

latches
A latch is designated by a rectangular block with
inputs on the left and outputs on the right. One
output designates the normal output, and the other
designates the complement output.

Flip-Flops
The state of a latch or flip-flop is switched by a
change in the control input. This momentary change
is called a trigger and the transition it cause is said to
trigger the flip-flop. The D latch with pulses in its
control input is essentially a flip-flop that is triggered
every time the pulse goes to the logic 1 level. As long
as the pulse input remains in the level, any changes
in the data input will change the output and the state
of the latch.

10

Clock Response in Latch

In Fig (a) a positive level response in the control
input allows changes, in the output when the D
input changes while the clock pulse stays at logic 1.

11

Clock Response in Flip-Flop

12

Edge-Triggered D FlipFlop
The first latch is called the master and the second
the slave. The circuit samples the D input and
changes its output Q only at the negative-edge of the
controlling clock.

D
Y
Q

110011
110011
? 1 1 0 0 1 .

CLK
13

D-Type Positive-Edge-Triggered FlipFlop

Another more efficient construction of an edgetriggered D flip-flop uses three SR latches. Two
latches respond to the external D(data) and
CLK(clock) inputs. The third latch provides the outputs
for the flip-flop.

Ref. p.175 texts

14

Graphic Symbol for EdgeTriggered D Flip-Flop

15

Other Flip-Flops
Flop

JK Flip-

There are three operations that can be performed

with a flip-flop: set it to 1, reset it to 0, or
complement its output. The JK flip-flop performs all
three operations. The circuit diagram of a JK flip-flop
constructed with a D flip-flop and gates.

16

JK Flip-Flop
The J input sets the flip-flop to 1, the K input resets it
to 0, and when both inputs are enabled, the output is
complemented. This can be verified by investigating
the circuit applied to the D input:
D = J Q` + K` Q

17

T Flip-Flop
The T(toggle) flip-flop is a complementing flip-flop
and can be obtained from a JK flip-flop when inputs
J and K are tied together.

18

T Flip-Flop
The T flip-flop can be constructed with a D flip-flop
and an exclusive-OR gates as shown in Fig. (b). The
expression for the D input is
D=T

Q = TQ` + T`Q

19

Characteristic
Equations
D flip-flop Characteristic Equations
Q(t + 1) = D
JK flip-flop Characteristic Equations
Q(t + 1) = JQ` + K`Q
T flip-flop Characteristic Equations
Q(t + 1) = T

Q = TQ` + T`Q
20

Direct Inputs
Some flip-flops have asynchronous inputs that are
used to force the flip-flop to a particular state
independent of the clock. The input that sets the flipflop to 1 is called present or direct set. The input that
clears the flip-flop to 0 is called clear or direct reset.
When power is turned on a digital system, the state
of the flip-flops is unknown. The direct inputs are
useful for bringing all flip-flops in the system to a
known starting state prior to the clocked operation.

21

D Flip-Flop with Asynchronous

Reset
A positive-edge-triggered D flip-flop with
asynchronous reset is shown in Fig(a).

22

D Flip-Flop with Asynchronous

Reset

23

Analysis of Clocked Sequential Circuits

The analysis of a sequential circuit consists of
obtaining a table or a diagram for the time sequence
of inputs, outputs, and internal states. It is also
possible to write Boolean expressions that describe
the behavior of the sequential circuit. These
expressions must include the necessary time
sequence, either directly or indirectly.

24

State Equations
The behavior of a clocked sequential circuit can be
described algebraically by means of state equations.
A state equation specifies the next state as a
function of the present state and inputs. Consider
the sequential circuit shown in Fig. 5-15. It consists
of two D flip-flops A and B, an input x and an output
y.

25

Fig.5-15 Example of Sequential

Circuit

26

State Equation
A(t+1) = A(t) x(t) + B(t)
x(t)
B(t+1) = A`(t) x(t)
A state equation is an algebraic expression that
specifies the condition for a flip-flop state transition.
The left side of the equation with (t+1) denotes the
next state of the flip-flop one clock edge later. The
right side of the equation is Boolean expression that
specifies the present state and input conditions that
make the next state equal to 1.
Y(t) = (A(t) + B(t)) x(t)`
27

State Table
The time sequence of inputs, outputs, and flip-flop
states can be enumerated in a state table
(sometimes called transition table).

28

State Diagram
The information available in a state table can be
represented graphically in the form of a state
diagram. In this type of diagram, a state is
represented by a circle, and the transitions between
states are indicated by directed lines connecting the
circles.
1/0 : means input =1
output=0

29

Flip-Flop Input
Equations
The part of the combinational circuit that
generates external outputs is descirbed algebraically
by a set of Boolean functions called output equations.
The part of the circuit that generates the inputs to
flip-flops is described algebraically by a set of
Boolean functions called flip-flop input equations. The
sequential circuit of Fig. 5-15 consists of two D flipflops A and B, an input x, and an output y. The logic
diagram of the circuit can be expressed algebraically
with two flip-flop input equations and an output
DA = Ax + Bx
equation:
DB = A`x
y = (A + B)x`
30

Analysis with D FlipFlop

The circuit we want to analyze is described by the
input equation DA = A
x
y
The DA symbol implies a D flip-flop with output A.
The x and y variables are the inputs to the circuit.
No output equations are given, so the output is
implied to come from the output of the flip-flop.

31

Analysis with D FlipFlop

The binary numbers under Axy are listed from 000
through 111 as shown in Fig. 5-17(b). The next state
values are obtained from the state equation A(t+1)
=A
x
y
The state diagram consists of two circles-one for
each state as shown in Fig. 5-17(c)

32

Analysis with JK Flip-Flops

33

Analysis with JK FlipFlop

The circuit can be specified by the flip-flop input
equations JA = B
KA = Bx`
JB = x`
KB = A`x + Ax` = A
x

34

Analysis with JK FlipFlops

A(t + 1) = JA` + K`A
B(t + 1) = JB` + K`B
Substituting the values of JA and KA from the input
equations, we obtain the state equation for A:
A(t + 1) = BA` + (Bx`)`A = A`B + AB` +Ax
The state equation provides the bit values for the
column under next state of A in the state table.
Similarly, the state equation for flip-flop B can be
derived from the characteristic equation by
substituting the values of JB and KB:
35

Analysis with JK FlipFlops

The state diagram of the sequential circuit is shown
in Fig. 5-19.

36

Analysis With T FlipFlops

Characteristic equation
Q(t + 1) = T
Q = T`Q +
TQ`
00/0 : means
state is 00
output is 0

37

Analysis With T Flip-Flops

Consider the sequential circuit shown in Fig. 5-20.

It has two flip-flops A and B, one input x, and one
output y. It can be described algebraically by two
input equations and an output equation:
Use present state
as inputs

TA = Bx
TB = x
y = AB
A(t+1)=(Bx)A+(Bx)A
=AB+Ax+ABx
B(t+1)=xB

38

Synthesis Using T FlipFlops

39

Registers and
TheCounter
filp-flops are essential component
in clocked sequential circuits.

Circuits that include filp-flops are

usually classified by the function they
perform. Two such circuits are registers
and counters.

An n-bit register consists of a group of n

flip-flops capable of storing n bits of
binary information.
40

Registers

In its broadest definition, a register

consists a group of flip-flops and gates
that effect their transition.

The flip-flops hold the binary information.

The gates determine how the information is
transferred into the register.

Counters are a special type of register.

A counter goes through a predetermined
sequence of states.

41

Registers

Fig 6-1 shows a

register constructed
with four D-type
filpflops.
Clock triggers all
flip-folps on the
positive edge of each
pulse.
Clear is useful for
clearing the register
to all 0s prior to its
clocked operation.
42

Register with
Parallel
Load
A clock edge applied to the C inputs of the

register of Fig. 6-1 will load all four inputs in

parallel.
For synchronism, it is advisable to control
the operation of the register with the D
inputs rather than controlling the clock in
the C inputs of the flip-flops.
A 4-bit register with a load control input that
is directed through gates and into the D
inputs of the flip-flops si shown in Fig. 6-2.

43

Register with
Parallel Load

44

Register with
Parallel
Load
When the load input is 1 , the data in the

four inputs are transferred into the register

with next positive edge of the clock.
When the load input is 0 ,the outputs of the
flip-flops are connected to their respective
inputs.
The feedback connection from output to
input is necessary because the D flip-flops
does not have a no change condition.

45

Shift Registers

A register capable of shifting its binary

information in one or both direction is
called a shift register.
All flip-flops receive common clock
pulses, which activate the shift from one
stage to the next.
The simplest possible shift register is
one that uses only flip-flops, as shown in
Fig. 6-3.

46

Shift Registers

47

Shift Registers

Each clock pulse shifts the contents

of the register one bit position to
the right.
The serial input determines what
goes into the leftmost flip-flop
during the shift.
The serial output is taken from the
output of the rightmost flip-flop.
48

Serial Transfer

A digital system is said tp operate in a serial

mode when information is transferred and
manipulated one bit at a time.
This in contrast to parallel transfer where all
the bits of the register are transferred at the
same time.
The serial transfer us done with shift
registers, as shown in the block diagram of
Fig. 6-4(a).

49

Serial Transfer

50

Serial Transfer

To prevent the loss of information stored in

the source register, the information in
register A is made to circulate by
connecting the serial output to its serial
input.
The shift control input determines when and
how many times the registers are shifted.
This is done with an AND gate that allows
clock pulses to pass into the CLK terminals
only when the shift control is active. [Fig. 64(a)].

51

Serial Transfer

52

Serial Transfer

The shift control signal is

synchronized with the clock and
changes value just after the
negative edge of the clock.
Each rising edge of the pulse causes
a shift in both registers. The fourth
pulse changes the shift control to 0
and the shift registers are disabled.

53

Serial Transfer
Table 6-1
Serial-Transfer Example

Timing Pulse

Shift Register
A

Shift Register
B

Initial value

1011

0010

After T1

1101

1001

After T2

1110

1100

After T3

0111

0110

After T4

1011

1011
54

Serial Transfer

In the parallel mode, information is

available from all bits can be
transferred simultaneously during one
clock pulse.
In the serial mode, the registers have a
single serial input and a single serial
output. The information us transferred
one bit at a time while the registers are
shifted in the same direction.

55

Serial Addition

Operations in digital computers are

usually done in parallel because this is a
faster mode of operation.
Serial operations are slower, but have the
advantage of requiring less equipment.
The two binary numbers to be added
serially are stored in two shift registers.
Bits are added one pair at a time through
a single full adder. [Fig. 6-5]

56

Serial Addition

57

Serial Addition

By shifting the sum into A while the bits

of A are shifted out, it is possible to use
one register for storing both the augend
and sum bits.
The carry out of the full adder is
transferred to a D flip-flop.
The output of the D flip-flop is then used
as carry input for the next pair of
significant bits.

58

Serial Addition

To show that serial operations can be

designed by means of sequential circuit
procedure, we will redesign the serial adder
using a state table.
The serial outputs from registers are
designated by x and y.
The sequential circuit proper has two inputs,
x and y, that provide a pair of significant bits,
an output S that generates the sum bit, and
flip-flop Q for storing the carry. [Table. 6-2]

59

Serial Addition
Table 6-2
State Table for serial Adder

Present
State

Inputs

Next State

Output

Flip-Flop
Inputs

JQ

KQ

60

Serial Addition

The two flip-flop input equations and

the output equation can be
simplified by means of map to obtain

JQ=xy
KQ=xy=(x+y)
S=xyQ

The circuit diagram is shown in [Fig.

6-6]

61

Serial Addition

62

Universal Shift
Register
A clear control to clear the register to 0.

A clock input to synchronize the

operations.
A shift-right control to enable the shift
operation and the serial input and output
lines associated with the shift right.
A shift-left control to enable the shift
operation and the serial input and output
lines associated with the shift left.

63

Universal Shift
Register
A parallel-load control to enable a parallel

transfer and the n input lines associated with

the parallel transfer.
n parallel output lines.
A control state that leaves the information in
the register unchanged in the presence of the
clock.
If the register has both shifts and parallel load
capabilities, it is referred to as a universal shift
register.

64

Universal Shift
Register

65

Universal Shift Register

Table 6-3
Function Table for the Register of Fig. 6-7

Mode Control
S1

S0

0
0
1

0
1
0

Register
Operation

No Change
Shift right
Shift Left

66

Universal Shift
Register
Shift registers are often used to

interface digital system situated

remotely from each other.
If the distance is far, it will be expensive
to use n lines to transmit the n bits in
parallel.
Transmitter performs a parallel-to-serial
conversion of data and the receiver
does a serial-to-parallel conversion.

67

Ripple Counters

A register that goes through a prescribed

sequence of states upon the application
of input pulse is called a counter.
A counter that follows the binary number
sequence is called a binary counter.
Counters are available in two categories

Ripple counters
Synchronous counters

68

Binary Ripple
Counter
The output of each flip-flop is connected to

the C input of the next flip-flop in sequence.

The flip-flop holding the last significant bit
receives the incoming count pulse.
A complementing flip-flop can be obtained
from:

JK flip-flop with the J and K inputs tied together.

T flip-flop
D flip-flop with the complement output
connected to the D input. [Fig. 6-8]

69

Binary Ripple
Counter

70

Binary Ripple Counter

Table 6-3
Function Table for the Register of Fig. 6-7

A3

A2

A1

A0

71

BCD Ripple Counter

A decimal counter follows a sequence of

ten states and returns to 0 after the
count of 9.
This is similar to a binary counter,
except that the state after 1001 is
0000.
The operation of the counter can be
explained by a list of conditions for flipflop transitions.

72

BCD Ripple Counter

73

BCD Ripple Counter

The four outputs are

designated by the
letter symbol Q with
a numeric subscript
equal to the binary
weight of the
corresponding bit in
the BCD code.

74

BCD Ripple Counter

The BCD counter of [Fig. 6-9] is a

decade counter.
To count in decimal from 0 to 999, we
need a three-decade counter. [Fig. 6-11]
Multiple decade counters can be
constructed by connecting BCD
counters ic cascade, one for each
decade.

75

BCD Ripple Counter

76

Synchronous
Counters
Synchronous counters are different

from ripple counters in that clock

pulses are applied to the inputs of
all flip-flops.
A common clock triggers all flipflops simultaneously rather than
one at a time in succession as in a
ripple counter.
77

Binary Counter

The design of a
synchronous binary
counter is so simple
that is no need to go
through a sequential
logic design process.
Synchronous binary
counters have a regular
pattern and can be
constructed with
complementing flip-flop
and gates
78

Up-Down Binary Counter

The two operations

can be combined in
one circuit to form a
counter capable of
counting up or
down.
It has an up control
input and down
control input.

79

BCD Counter

Because of the return to 0 after a

count of 9, a BCD counter does not
have a regular pattern as in a
straight binary count.
To derive the circuit of a BCD
synchronous counter, it is
necessary to go through a
sequential circuit design procedure.
80

BCD Counter
Table 6-5
State Table for BCD Counter
Present State

Next State

Output

Flip-Flop inputs

Q8

Q4

Q2

Q1

Q8

Q4

Q2

Q1

TQ8

TQ4

TQ2

TQ1

1
81

BCD Counter

The flip flop input equations can be

simplified by means of maps. The
simplified functions are

TQ1=1
TQ2=Q8Q1
TQ4=Q2Q1
TQ8=Q8Q1+Q4Q2Q1
y=Q8Q1

The circuit can be easily drawn with four T

flip-flops, five AND gates, and one OR gate.

82

Binary Counter with

Parallel
Load

Counters employed in digital systems

quite often require a parallel load
capability for transferring an initial
binary number into the counter prior to
count operation.
The input load control when equal to 1
disables the count operation and causes
a transfer of data from the four data
inputs into the four flip-flops [Fig. 6-14]

83

Binary Counter with

Parallel Load

84

Binary Counter with Parallel

Load
Table 6-6
Function Table for the Counter of Fig. 6-14

Clear

CLK

Load

Count

Function

Clear to 0

Load inputs

Count next binary

state

No change

85

Binary Counter with

Parallel Load

A counter with parallel load can be

used to generate any desire count
sequence.
[Fig.6-15] shows two ways in which
a counter with parallel load is used
to generate the BCD count.

86

Binary Counter with

Parallel Load

87

End of Unit-4

88