8085

INTERRUPTS
1

INTERRUPTS

When a microprocessor is interrupted, it stops

executing its current program and calls a special
routine which services the interrupt
The event that causes the interruption is called
Interrupt
The special routine executed to service the
interrupt is called ISR - Interrupt Service
Routine/Procedure
2

INTERRUPT CLASSIFICATION

Hardware Interrupt An interrupt caused by an External signal

Software Interrupt An interrupt caused by Special Instruction

Maskable Interrupts Can be delayed or Rejected

Non-Maskable Interrupts Can not be delayed or Rejected

(Service must)

Vectored Where the subroutine starts is referred to as

Vector Location
Non-vectored The address of the service routine needs to
be supplied externally by the device

8085 INTERRUPTS
TRAP
RST7.5
RST6.5
RST 5.5
INTR

8085

INTA

The EI instruction is a one byte instruction and is used

to Enable the maskable interrupts.
The DI instruction is a one byte instruction and is used
to Disable the maskable interrupts.

Interrupt Name

Maskable

Vectored

INTR

Yes

No

RST 5.5

Yes

Yes

RST 6.5

Yes

Yes

RST 7.5

Yes

Yes

TRAP

No

Yes

INTERRUPT VECTORS & THE VECTOR

TABLE
An interrupt vector is a pointer to where the
ISR is stored in memory.
All interrupts (vectored or otherwise) are
mapped onto a memory area called the
Interrupt Vector Table (IVT).

The

IVT is usually located in (0000H - 00FFH).

Vector Address = Interrupt number * 8

Calculation

Vector
Address

INTR

--

--

TRAP ( RST 4.5)

4.5x8=36

0024H

RST 5.5

5.5x8=44

002CH

RST 6.5

6.5x8=52

0034H

RST 7.5

7.5x8=60

003CH

Interrupt Name

8085 INTERRUPTS SUMMARY

Interrupt Triggering

Priorit

Name

Method

TRAP

Edge &

1st

RST 4.5
RST 7.5
RST 6.5

RST 5.5

INTR

Level

Sensitive
Edge
Sensitive
Level

Sensitive
Level

Sensitive
Level

Sensitive

Highest
2nd
3

rd

th

5th
Lowest

Maskable
No
Yes
Yes

Yes

Yes

Masking

Vector

Method

Address

None

0024H

DI / EI

003CH

SIM
DI / EI

0034H

SIM
DI / EI

002CH

SIM
Pin
( INTR &
INTA)

-8

SOFTWARE INTERRUPT

The 8085 recognizes 8 RESTART instructions:

RST n ( RST0 - RST7)
Each

of these would send the execution to a redetermined

hard-wired memory location:
Restart
Instruction

Vector
Address

RST 0

CALL 0000H

RST 1

CALL 0008H

RST 2

CALL 0010H

RST 3

CALL 0018H

RST 4

CALL 0020H

RST 5

CALL 0028H

RST 6

CALL 0030H

RST 7

CALL 0038H

THE 8085 MASKABLE/VECTORED

INTERRUPT PROCESS
1.
2.
3.

4.

The interrupt process should be enabled using

the EI instruction.
The 8085 checks for an interrupt during the
execution of every instruction.
If there is an interrupt, and if the interrupt is
enabled using the interrupt mask, the
microprocessor will complete the executing
instruction, and reset the interrupt flip flop.
The microprocessor then executes a call
instruction that sends the execution to the
appropriate location in the interrupt vector
table.

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THE 8085 MASKABLE/VECTORED

INTERRUPT PROCESS
5.

6.
7.

8.

When the microprocessor executes the call

instruction, it saves the address of the next
instruction on the stack.
The microprocessor jumps to the specific
service routine.
The service routine must include the
instruction EI to re-enable the interrupt
process.
At the end of the service routine, the RET
instruction returns the execution to where the
program was interrupted.

11

SIM SERIAL INTERRUPT MASK

6

5 4

SDO
SDE
XXX
R7.5
MSE
M7.5
M6.5
M5.5

Serial Data Out

Either 0 or 1

Enable Serial Data

0 - Disable
1 - Enable

Not Used

RST5.5 Mask
RST6.5 Mask
RST7.5 Mask

0 - Available
1 - Masked

Mask Set Enable

0 - Ignore bits 0-2
1 - Set the masks according
to bits 0-2

Force RST7.5 Flip Flop to reset

SIM VALUE MUST BE LOADED IN

ACCUMULATOR

12

Example
MSE Mask Set Enable
RST 6.5 Mask
RST 5.5 & 7.2 Unmask
RST FF Dont Reset
Serial Data Igonered

SDO
SDE
XXX
R7.5
MSE
M7.5
M6.5
M5.5

0 0 0 0 1 0 1 0
Contents of accumulator are: 0AH
EI
MVI A, 0A
SIM

; Enable interrupts including INTR

; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5
; Apply the settings RST masks

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Example
MSE Mask Set Disable
RST FF Reset
Serial Data Enable
Serial Data output is 0
SDO
SDE
XXX
R7.5
MSE
M7.5
M6.5
M5.5

0 1 0 1 0 1 0 0
Contents of accumulator are: 54H

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RIM READ INTERRUPT MASK

5 4

SDI
P7.5
P6.5
P5.5
IE
M7.5
M6.5
M5.5

Serial Data In
RST5.5 Interrupt Pending
RST6.5 Interrupt Pending
RST7.5 Interrupt Pending

RST5.5 Mask
RST6.5 Mask
RST7.5 Mask

0 - Available
1 - Masked

Interrupt Enable
Value of the Interrupt Enable
Flip Flop

Set 1
Reset - 0

COPIES THE STATUS OF THE INTERRUPTS INTO THE

ACCUMULATOR

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Example
Interrupt Enable
RST 5.5 & 6.5 Masked
RST 7.5 Pending
Serial Input Data is 0
SID
P7.5
P6.5
P5.5
IE
M7.5
M6.5
M5.5

0 1 0 0 1 0 1 1
Contents of accumulator are: 4BH

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