The 8051 Microcontroller

Microprocessor vs. Microcontroller

Microprocessor
CPU is stand-alone, RAM,
ROM, I/O, timer are separate
designer can decide on the
amount of ROM, RAM and
I/O ports.
expansive
versatility
general-purpose

Microcontroller
CPU, RAM, ROM, I/O and
timer are all on a single chip
fix amount of on-chip ROM,
RAM, I/O ports
Highly bit addressable
for applications in which cost,
power and space are critical
single-purpose

Advantages of Microcontroller
based System

As the peripherals are integrated into a single chip, the overall

system cost is very less
The product is of small size compared to micro processor based
system
The system design now requires very little efforts
As the peripherals are integrated with a microprocessor the
system is more reliable
Though microcontroller may have on chip ROM,RAM and I/O
ports, addition ROM, RAM I/O ports may be interfaced
externally if required
On chip ROM provide a software security
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Comparison of the 8051 Family

Members

ROM type

8031
80xx
87xx
89xx

no ROM
mask ROM
EPROM
Flash EEPROM

89xx

8951
8952
8953
8955
898252
891051
892051

Example (AT89C51,AT89LV51)
AT= ATMEL(Manufacture)
C = CMOS technology
LV= Low Power(3.0v)

Comparison some of the 8051 Family

Members
ROM

RAM

Timer

8051

4k

128

8031

128

8751

4k eprom

128

8052

8krom

256

8032

256

8752

8k eprom

256

8051 Basic Component

4K bytes internal ROM

128 bytes internal RAM
Four 8-bit I/O ports (P0 - P3).
Two 16-bit timers/counters
One serial interface
64k external memory for code
64k external memory for dataMicrocontroller

The basic 8051 Core

8-bit CPU optimized for control applications
Capability for single bit Boolean operations.
Supports up to 64K of program memory.
Supports up to 64K of data memory.
4 K bytes of on-chip program memory.
Newer devices provide more.
128bytes of on-chip data RAM
Four 8 bit ports.
Two 16-bit timer/counters
Interrupts
On-chip clock oscillator
7

Block Diagram
External interrupts
Interrupt
Control

On-chip
ROM for
program
code

Timer/Counter

On-chip
RAM

Timer 1
Timer 0

CPU

OSC

Bus
Control

4 I/O Ports

P0 P1 P2 P3

Address/Data

Serial
Port

TxD RxD

Counter
Inputs

8051 Internal Block Diagram

8051
Schematic
Pin out

8051
Foot Print

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
(T0)P3.4
(T1)P3.5
(WR)P3.6
(RD)P3.7
XTAL2
XTAL1
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

8051
(8031)
(8751)
(8951)

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Vcc
P0.0(AD0
)P0.1(AD1)
P0.2(AD2
) 0.3(AD3)
P
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14
)P2.5(A13
)P2.4(A12
)P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)

Port 0 with Pull-Up Resistors

Vcc

Port 0

P0.0
DS5000 P0.1
P0.2
8751
P0.3
P0.4
8951
P0.5
P0.6
P0.7

10 K

IMPORTANT PINS (IO Ports)

One of the most useful features of the 8051 is that it contains
four I/O ports (P0 - P3)
Each port can be used as input or output (bi-direction)

Port 0
pins 32-39 P0.0 P0.7

8-bit R/W - General

Purpose I/O
Or acts as a multiplexed
low byte address and data
bus for external memory
design

IMPORTANT PINS (IO Ports)

Port 1
pins 1-8 P1.0
P1.7

Only 8-bit R/W General Purpose I/O

IMPORTANT PINS (IO Ports)

Port 2
pins 21-28 P2.0
P2.7

8-bit R/W General Purpose

I/O
Or high byte of
the address bus
for external
memory design

IMPORTANT PINS (IO Ports)

Port 3
pins 10-17 P3.0
P3.7

General Purpose I/O

if not using any of the
internal peripherals
(timers) or external
interrupts.

Port 3 Alternate Functions

 ALE

- Address latch enable

to select valid address
EA/Vpp - External access enable
EA-0 execute program in external
memory
EA-1 execute program in internal
memory
Vpp it receives 21 V for on chip EPROM
PSEN Program store enable
store to read the external program memory

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Registers
A
B
R0

DPTR

DPH

DPL

R1
R2

PC

PC

R3
R4
R5
R6
R7
Some 8-bitt Registers of
the 8051

Some 8051 16-bit Register

SJCET

SJCET

SJCET

Parallel I/O Ports

Each port can be input or output

Port0
latch

Port1
latch

Port2
latch

Port3
latch

Port0

Port1

Port2

Port3

DPTR
The data pointer consists of a high
byte(DPH) and a low byte (DPL). Its
function is to hold a 16 bit address. It
may be manipulated as a 16 bit data
register or two independent 8 bit
register. It serves as a base register in
indirect jumps, lookup table instructions
and external data transfer.
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Stack in the 8051

7FH

The register used to access

the stack is called SP
(stack pointer) register.

Scratch pad RAM

30H
2FH

The stack pointer in the

8051 is only 8 bits wide,
which means that it can
take value 00 to FFH.
When 8051 powered up,
the SP register contains
value 07.

Bit-Addressable RAM
20H
1FH
18H
17H
10H
0FH
08H
07H
00H

Register Bank 3
Register Bank 2
Register Bank 1( Stack)
Register Bank 0

Memory Organization
The 8051 memory organization is rather complex.
The 8051 has separate address spaces for Program Memory, Data
Memory, and external RAM.
This is refereed to as a Harvard architecture.
The early Mark I (1944) computer developed at Harvard was of this
type of architecture.
Von Neumann at Princeton pointed out that it was not necessary to put
instructions and data in separate memories.
Most machines have been Princeton architecture.
Recently Harvard architecture has been employed to help alleviate the
memory bottleneck.
Both program memory and external data memory are 8 bits wide and use
16 bits of address. The internal data memory is accessed using an 8-bit
address.

Data Memory (DM)

Intel 8051: Timers/Counters

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Timer

Timer/Counter Mode Control Register TMOD

A timer is a counter that is

increased with every time an
instruction is executed e.g.
8051 with 12MHz increases a
counter every 1.000 s
General 8051 has 2 timer:

2 16-bit timer

Timer/Counter Control Register TCON

TMOD Register:

Gate : When set, timer only runs while INT(0,1) is

C/T : Counter/Timer select bit.
M1 : Mode bit 1.
M0 : Mode bit 0.

high.

TCON Register:

TF: Overflow flag

Set by hardware on Timer/Counter overflow
Cleared by hardware when processor vectors to interrupt routine
TR: Run control bit
Set/Cleared by software to turn Timer/Counter on/off
IE: Interrupt Edge flag
Set by hardware when external interrupt edge detected
Cleared when interrupt processed
IT: Interrupt Type control bit
Set/Cleared by software to specify
falling edge/low level triggered external interrupts

TF1: Timer 1 overflow flag.

TR1: Timer 1 run control bit.
TF0: Timer 0 overflag.
TR0: Timer 0 run control bit.
IE1: External interrupt 1 edge flag. IT1: External interrupt 1 type flag.
IE0: External interrupt 0 edge flag. IT0: External interrupt 0 type flag.

Serial Communication
Computers transfer data in two ways:
Parallel: Often 8 or more lines (wire conductors)
are used to transfer data to a device that is only a
few feet away.
Serial: To transfer to a device located many meters
away, the serial method is used. The data is sent
one bit at a time.

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Continued
Serial data communication uses two methods
Synchronous method transfers a block of data at a time
Asynchronous method transfers a single byte at a time
There are special ICs made by many manufacturers for
serial communications.
UART (universal asynchronous Receiver transmitter)
USART (universal synchronous-asynchronous
Receiver-transmitter)

Registers related to Serial

Communication

1. SBUF Register
2. SCON Register
3. PCON Register

SBUF Register
SBUF is an 8-bit register
communication.

used solely for serial

For a byte data to be transferred via the TxD line, it must be

placed in the SBUF register.
The moment a byte is written into SBUF, it is framed with the
start and stop bits and transferred serially via the TxD line.
SBUF holds the byte of data when it is received by 8051 RxD
line.
When the bits are received serially via RxD, the 8051
deframes it by eliminating the stop and start bits, making a
byte out of the data received, and then placing it in SBUF.

SCON Register
SM0 SM1 SM2 REN TB8 RB8 TI

Set to Enable
Serial Data
reception

RI

Set when a Charactor received

Set when Stop bit Txed

9th Data Bit

Enable Multiprocessor 9th Data Bit
Communication Mode Sent in Mode 2,3 Received in Mode 2,3

INTERRUPTS

Steps in Executing an Interrupt

1. It finishes the instruction it is executing and saves the address of the
next instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e: not
on the stack).
3. It jumps to a fixed location in memory, called the interrupt vector
table, that holds the address of the ISR.
4. The microcontroller gets the address of the ISR from the interrupt
vector table and jumps to it.
5. It starts to execute the interrupt service subroutine until it reaches the
last instruction of the subroutine which is RETI (return from
interrupt).
6. Upon executing the RETI instruction, the microcontroller returns to
the place where it was interrupted.
8051 Microcontroller

Suresh.P.Nair , HOD - ECE , RCET

39

Six Interrupts in 8051

Six interrupts are allocated as follows:
1. Reset power-up reset.
2. Two interrupts are set aside for the timers.
one for timer 0 and one for timer 1
3. Two interrupts are set aside for hardware external
interrupts.
P3.2 and P3.3 are for the external hardware
interrupts INT0 (or EX1), and INT1 (or EX2)
4. Serial communication has a single interrupt that belongs
to both receive and transfer.

What events can trigger Interrupts?

We can configure the 8051 so that any of the following
events will cause an interrupt:

Timer 0 Overflow.
Timer 1 Overflow.
Reception/Transmission of Serial Character.
External Event 0.
External Event 1.

We can configure the 8051 so that when Timer 0

Overflows or when a character is sent/received, the
appropriate interrupt handler routines are called.

8051 Interrupt Vectors

8051 Interrupt related Registers

The various registers associated with the use of interrupts
are:
TCON - Edge and Type bits for External Interrupts 0/1
SCON - RI and TI interrupt flags for RS232
IE - Enable interrupt sources
IP - Specify priority of interrupts

Enabling and Disabling an Interrupt

Upon reset, all interrupts are disabled (masked), meaning
that none will be responded to by the microcontroller if
they are activated.
The interrupts must be enabled by software in order for
the microcontroller to respond to them.
There is a register called IE (interrupt enable) that is
responsible for enabling (unmasking) and disabling
(masking) the interrupts.

Interrupt Enable (IE) Register

- EA : Global enable/disable.
---

: Reserved for additional interrupt hardware.

ES : Enable Serial port interrupt.

ET1 : Enable Timer 1 control bit.
EX1 : Enable External 1 interrupt.
ET0 : Enable Timer 0 control bit.
EX0 : Enable External 0 interrupt.

Interrupt Priority
When the 8051 is powered up, the priorities are assigned
according to the following.
In reality, the priority scheme is nothing but an internal polling
sequence in which the 8051 polls the interrupts in the sequence
listed and responds accordingly.

Interrupt Priority
We can alter the sequence of interrupt priority by assigning
a higher priority to any one of the interrupts by
programming a register called IP (interrupt priority).
To give a higher priority to any of the interrupts, we make
the corresponding bit in the IP register high.

Interrupt Priority (IP) Register

Reserved

PS PT1 PX1

PT0

PX0

Serial Port
Timer 1 Pin
INT 1 Pin
Priority bit=1 assigns
high priority
Priority bit=0 assigns

INT 0 Pin
Timer 0 Pin

Types of Microcontrollers

THANK YOU

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