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Obvious reasons
I - Introduction
I - Introduction
Scientific equipment
Embedded products
I - Introduction
its switching elements are vacuum tubes (a big advance from relays)
1945: John von Neumann develops the first stored program computer
I - Introduction
What is design?
I - Introduction
Collection of devices that sense and/or control wires that carry a digital
value (i.e., a physical quantity that can be interpreted
as a 0 or 1)
example: digital logic where voltage < 0.8v is a 0 and > 2.0v is a 1
example: pair of transmission wires where a 0 or 1 is distinguished by
which wire has a higher voltage (differential)
example: orientation of magnetization signifies a 0 or a 1
store a value
recall a previously stored value
sense
AND
I - Introduction
drive
7
Scale
Time
Cost
I - Introduction
New ability: to accomplish the logic design task with the aid of computer-ai
design tools and map a problem description into an implementation with
programmable logic devices after validation via simulation and understand
of the advantages/disadvantages as compared to a software implementati
I - Introduction
representation:
"0", "1" on a wire
set of wires (e.g., for binary ints)
assignment:
x = y
data operations:
x+y5
control:
sequential statements: A; B; C
conditionals:
if x == 1 then y
loops:
for ( i = 1 ; i == 10, i++)
procedures:
A; proc(...); B;
I - Introduction
10
Z
close switch (if A is 1 or asserted)
and turn on light bulb (Z)
Z
open switch (if A is 0 or unasserted)
and turn off light bulb (Z)
Z A
I - Introduction
11
Switches (contd)
Z A and B
A
OR
Z A or B
I - Introduction
12
Switching networks
Switch settings
I - Introduction
13
Relay networks
14
Transistor networks
I - Introduction
15
MOS transistors
G
D
n-channel
open when voltage at G is low
closes when:
voltage(G) > voltage (S) +
I - Introduction
p-channel
closed when voltage at G is low
opens when:
voltage(G) < voltage (S)
16
MOS networks
what is the
relationship
between x and y?
3v
Y
0v
I - Introduction
0 volts
3 volts
3 volts
0 volts
17
3v
Z1
0v
what is the
relationship
between x, y and z?
x
z1
z2
3v
Z2
0v
I - Introduction
18
I - Introduction
19
I - Introduction
20
I - Introduction
21
State 0
State 1
Relay logic
Circuit Open
Circuit Closed
CMOS logic
0.0-1.0 volts
2.0-3.0 volts
Transistor transistor logic (TTL)
0.0-0.8 volts 2.0-5.0 volt
Fiber Optics
Light off
Light on
Dynamic RAM
Discharged capacitor
Charged ca
Nonvolatile memory (erasable)
Trapped electrons
No
Programmable ROM
Fuse blown
Fuse intact
Bubble memory
No magnetic bubble
Bubble pres
Magnetic disk
No flux reversal
Flux reversal
Compact disc
No pit
Pit
I - Introduction
22
system
outputs
I - Introduction
23
Common combinational logic systems have standard symbols called logic gates
Buffer, NOT
AND, NAND
OR, NOR
A
B
A
B
I - Introduction
easy to implement
with CMOS transistors
(the switches we have
available and use most)
24
Sequential logic
Sequential systems
look at the outputs only after sufficient time has elapsed for the
system to make its required changes and settle down
I - Introduction
25
I - Introduction
26
Combinational:
input A, B
wait for clock edge
observe C
wait for another clock edge
observe C again: will stay the same
A
C
B
Sequential:
Clock
input A, B
wait for clock edge
observe C
wait for another clock edge
observe C again: may be different
I - Introduction
27
Abstractions
I - Introduction
28
An example
I - Introduction
29
Implementation in software
integer number_of_days ( month, leap_year_flag)
{
switch (month) {
case 1: return (31);
case 2: if (leap_year_flag == 1) then return (29)
else return (28);
case 3: return (31);
...
case 12: return (31);
default: return (0);
I - Introduction
30
Implementation as a
combinational digital system
Encoding:
Behavior:
combinational
truth table
specification
month
leap
0010
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
111
leap
0
1
d28
0
1
0
0
0
0
0
0
0
0
0
0
0
d29
0
0
1
0
0
0
0
0
0
0
0
0
0
d30
0
0
0
0
1
0
1
0
0
1
0
1
0
d31
1
0
0
1
0
1
0
1
1
0
1
0
1
d28d29d30d31
I - Introduction
31
symbol
for not
0
0
0
1
symbol
for and
I - Introduction
symbol
for or
0010
0010
0011
0100
...
1100
1101
111
0000
0
1
1
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
32
d28 = m8'm4'm2m1'leap
d29 = m8'm4'm2m1'leap
d30 = (m8'm4m2'm1') + (m8'm4m2m1') +
(m8m4'm2'm1) + (m8m4'm2m1)
= (m8'm4m1') + (m8m4'm1)
d31 = (m8'm4'm2'm1) + (m8'm4'm2m1) +
(m8'm4m2'm1) + (m8'm4m2m1) +
(m8m4'm2'm1') + (m8m4'm2m1') +
(m8m4m2'm1')
I - Introduction
33
Activity
m8 is 0 and m1 is 1, or m8 is 1 and m1 is 0
d31 = m8m1 + m8m1
34
d28 = m8'm4'm2m1'leap
d29 = m8'm4'm2m1'leap
d30 = (m8'm4m2'm1') + (m8'm4m2m1') +
(m8m4'm2'm1) + (m8m4'm2m1)
d31 = (m8'm4'm2'm1) + (m8'm4'm2m1) +
(m8'm4m2'm1) + (m8'm4m2m1) +
(m8m4'm2'm4') + (m8m4'm2m1') +
(m8m4m2'm1')
I - Introduction
35
Another example
I - Introduction
36
Implementation in software
integer combination_lock ( ) {
integer v1, v2, v3;
integer error = 0;
static integer c[3] = 3, 4, 2;
while (!new_value( ));
v1 = read_value( );
if (v1 != c[1]) then error = 1;
while (!new_value( ));
v2 = read_value( );
if (v2 != c[2]) then error = 1;
while (!new_value( ));
v3 = read_value( );
if (v2 != c[3]) then error = 1;
if (error == 1) then return(0); else return (1);
}
I - Introduction
37
Implementation as a sequential
digital system
Encoding:
Behavior:
I - Introduction
new
value
reset
state
open/closed
38
Finite-state diagram
states: 5 states
ERR
closed
C1!=value
& new
S1
reset
closed
closed
C1=value
& new
not new
I - Introduction
S2
C2!=value
& new
S3
C3!=value
& new
closed
C2=value
& new
not new
OPEN
open
C3=value
& new
not new
39
Internal structure
data-path
control
new
value
C1
C2
multiplexer
C3
mux
control
equal
reset
controller
clock
comparator
equal
I - Introduction
open/closed
40
Finite-state machine
reset
not equal
not equal
& new
& new
S1
S2
S3
OPEN
closed
closed
closed
open
mux=C1 equal mux=C2 equal mux=C3 equal
& new
& new
& new
not new
I - Introduction
not new
not new
41
Finite-state machine
ERR
reset
1
0
0
0
0
0
0
0
0
0
0
0
new
0
1
1
0
1
1
0
1
1
I - Introduction
equal
0
1
0
1
0
1
state
S1
S1
S1
S2
S2
S2
S3
S3
S3
OPEN
ERR
next
state
S1
S1
ERR
S2
S2
ERR
S3
S3
ERR
OPEN
OPEN
ERR
not equal
not equal not equal
& new
& new
& new
S1
S2
S3
OPEN
closed
closed
closed
open
mux=C1 equal mux=C2 equal mux=C3 equal
& new
& new
& new
not new
mux
C1
C1
C2
C2
C3
C3
closed
not new
not new
open/closed
closed
closed
closed
closed
closed
closed
closed
closed
closed
open
open
closed
42
I - Introduction
43
choose 1 bits: 1, 0
reset
1
0
0
0
0
0
0
0
0
0
0
0
I - Introduction
new
0
1
1
0
1
1
0
1
1
equal
0
1
0
1
0
1
state
0001
0001
0001
0010
0010
0010
0100
0100
0100
1000
0000
next
state
0001
0001
0000
0010
0010
0000
0100
0100
0000
1000
1000
0000
mux
001
001
010
010
100
100
open/closed
0
0
0
good choice of encoding!
0
0
mux is identical to
0
last 3 bits of state
0
0
open/closed is
0
identical to first bit
1
of state
1
0
44
Activity
remove reset
not new
not new
E2
closed
not equal
& new
E3
new
not equal
& new
closed
new
ERR
closed
not equal
& new
S1
S2
S3
closed
closed
closed
mux=C1 equal mux=C2 equal mux=C3 equal
& new
& new
& new
not new
I - Introduction
not new
OPEN
open
not new
45
mux
control
equal
reset
controller
clock
comb. logic
state
clock
open/closed
I - Introduction
46
Design hierarchy
system
control
data-path
code
registers multiplexer comparator
register
state
registers
combinational
logic
logic
switching
networks
I - Introduction
47
Summary
I - Introduction
48