Programmable Devices:

8254 & 8259

Haris Ahmed
Mohd. Nauman
Ashutosh Chauhan
Md Azharuddin

Programmable Interval Timer

PITs perform timing & counting operations.
Can be used to produce time delays & are
used as real time clock , event counter etc.
Trivia: PIT is being used in IBM PC
compatibles since 1981.

Introducing 8254

The Intel 8254 is a programmable counter.

It includes 3 identical 16 bit counters.
It is packaged in a 24-pin DIP.
Six programmable modes.
Gate is used to enable or disable the
counter.

Trivia :Initially designed to work with Intel

80/85. Later, incorporated with x86 family.
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Architecture
Of 8254
D7-D0

RD
W
R
A0
A1
CS

DATA
BUS
BUFFE
R
READ/
WRITE
LOGIC

CONTROL
WORD
REGISTER

COUNTE
R
0

COUNTER
1

CLK 0
GATE 0
OUT 0

CLK 1
GATE 1
OUT 1

COUNTER
2

CLK 2
GATE 2
OUT 2
4

Into the world of 8254

Data Bus Buffer:
This block contains the logic to buffer the data bus to the
microprocessor and to the internal registers. It has 8 input
pins, usually labelled as D7..D0, where D7 is the MSB.

Control Logic:

The control section has five signals: Read, Write, Chip

select and the address lines A0 and A1.
In peripheral I/O mode read and write signals are
connected to IOR and IOW while in memory mapped
these are connected to MEMR and MEMW.

The control word register and counters are selected

according to signals on lines A0 and A1 as shown below:

CS A1
0
0
0
0
0
1
0
1

A0 Select
0
Counter 0
1
Counter 1
0
Counter 2
1
Control Reg.

Control word Register:

This register is accessed when lines A0 and A1
are at logic 1.
It is used to write command word which specifies
the counter to be used, its mode and either read
or write format.

8253/8254 word format

MODES OF 8254
MODE 0: Interrupt on terminal count.
MODE 1: Programmable 1 shot.
MODE 2: Rate generator.
MODE 3: Square wave generator.
MODE 4: Software triggered strobe.
MODE 5: Hardware triggered strobe.
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Modes of Operation
of 8254

Mode 0: Interrupt on Terminal Count

The output will start off zero. The count is loaded
and the timer will start to count down.
When the count has reached zero the output will
be set high, and remain high until the next count
has been reloaded.
This can be used as an interrupt.

Mode 1: Programmable One-Shot

The output will go low following the rising edge of
the gate input.
The counter will count and the output will go high
once the counter has reached zero.

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Mode 2: Rate Generator

This mode is used to generate a pulse equal to
the clock period at a given interval.
When count is loaded the OUT stays high until the
count reaches 1 and the the OUT goes low for one
clock period.
The count is reloaded automatically and the pulse
is generated continuously.

Mode 3: Square Wave Generator

This mode is similar to mode 2. However, the
duration of the high and low clock pulses of the
output will be different from mode 2.
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 Suppose n is the number loaded into the counter (the

COUNT message), the output will be:
high for n/2 counts, and low for n/2 counts, if n is even.
high for (n+1)/2 counts, and low (n-1)/2 for counts, if n
is odd

Mode 4: Software Triggered Pulse

The output will remain high until the timer has counted
to zero, at which point the output will pulse low and
then go high again.

Mode 5: Hardware Triggered Pulse

The counter will start counting once the gate input goes
high, when the counter reaches zero the output will
pulse low and then go high again.
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A Specific Peripheral Device That

Can Be Connected To 8086 to
manage complex interrupts
systems.
The 8259 Programmable
Interrupt Controller

8259 PIC

Programming 8259A

The 8259A accepts two types of command words generated

by the CPU:

1. Initialization Command Words (ICWs): Before normal

operation can begin, each 8259A in the system must be
brought to a starting point by a Sequence of 2 to 4 bytes
timed by WR pulses.

2. Operation Command Words (OCWs):

These are the
command words which command the 8259Ato operate in
various interrupt modes.

These modes are:

a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode

The OCWs can be written into the 8259A anytime after

initialization.

Initialization Command
Words

ICW Format
ICW 1:
A0
0

D7

D6

D5

D4

D3

A7

A6

A5

D2
LTIM

IC4=1 ICW4 needed

IC4=0 ICW4 not needed
SNGL=1 Single
SNGL=0
Cascade Mode
ADI=1
Interval of 4 bytes(8086)
ADI=0
Interval of 8 bytes
LTIM=1
Level Triggered Mode
LTIM=0
Edge Triggered Mode
A5-A7 Vector Addresses(dont care in 8086 mode)

D1
ADI

D0
SNGL IC 4

 ICW 2:
A0

D7

D6

D5

D4

D3

D2

D1

D0
1
A8

A15/T7 A14/T6 A13/T5 A12/T4 A11/T3

A10

A9

A8 A15
(VECTOR ADDRESSES in case of MCS 80/85 system)
T3-T7
(five most significant bits of interrupt typeof MCS 8086/8088
system)

 ICW 3: (MASTER MODE)

A0
1 S7

D7
S6

D6
S5

D5

D4

S4

D3

D2

S3

S2

D1
S1

D0
S0

S0 S7 = 1, IR input has a slave

= 0, IR input does not have a slave

ICW 3: (SLAVE MODE)

A0
1
ID0

D7

D6

D5

D4

D3

ID0-2 = Slave IDs

D2

D1

D0

ID2

ID1

 ICW 4:
A0
1

D7
0

D6
0

D5
0

D4
D3
D2
D1
D0
SFNM BUF M/S AEOI mPM

mPM=1 8085 selected

=0 8086 selected
AEOI=1
Automatic end of interrupt mode selected
M/S=1
8259A is a master(BUF=1)
=0
8259A is a slave(BUF=1)
BUF=1
buffered mode selected
SFNM=1
special fully nested mode selected

Operation Command Words

(OCW)
OCW1: A0
1

D7 D6 D5 D4 D3 D2 D1 D0
M7 M6 M5 M4 M3 M2 M1 M0

Interrupt Mask = 1 Mask Set

= 0 Mask Reset

 OCW 2:

A0

D7

D6

1
L0

D5
R

0
0
1

D4
SL

0
1
0

D3

EOI

D2
0

D1
0

D0

L2

1
1
1

- Non-Specific EOI Command

- Specific EOI Command
- Rotate on Non-Specific EOI

- Rotate in automatic EOI

Command

1
0
mode (Set)
0
0
0

- Rotate in automatic EOI mode

(Clear)

1
1
command
1
1

L1

- Rotate on Specific EOI

- Set Priority Command*

 OCW 3 :

A0

D7

0
RIS

D6

D5
0

D4

D3

ESMM SMM

D2
0

D1

D0
P

No Action 0
0
No Action 0
1
Read interrupt request Reg. reg. on next RD pulse 1
Read interrupt service reg. on next RD pulse 1
1
P =1 Poll Command
=0 No Poll Command
ESMM SMM
0
0
1
1

0
1
0
1

No Action
No Action
Reset Special Mask
Set Special Mask

RR

OCW Description
OCW 3 : ESMM (Enable Special Mask Mode) - When this
bit is set to 1 it enables the SMM bit to set or
reset the Special Mask Mode. When ESMM is 0 the
SMM bit becomes a ``don't care''.
SMM (Special Mask Mode) - If ESMM = 1 and SMM
= 1 the 8259A will enter Special Mask Mode. If
ESMM = 1 and SMM = 0 the 8259A will revert to
normal mask mode. When ESMM = 0, SMM has
no effect.

Operating modes of 8259

Fully nested mode

End of interrupt(EIO)
Automatic rotation
Automatic EIO mode
Specific rotation
Special mask mode
Edge and level triggered mode
Poll command mode
Cascade mode

Cascader Mode

References

http://www.circuitstoday.com/
http://www.ti.com/lit/an/slyt145/slyt145.pdf
http://
8085projects.info/page/free-programs-for-8085-microproc
essor.html
http://www.learnabout-electronics.org/index.php
https://www.youtube.com/watch?v=nxAQ1PFEd5U

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THANK YOU!