PSEUDO CMOS:

A DESIGN STYLE FOR

LOW COST AND ROBUST
FLEXIBLE ELECTRONICS
BY
V.JYOSTHNA(13311D0616)
GUIDE: C.N. SUJATHA

Objective

To increase
To design

carrier mobility

flexible electronic circuits

Disadvantages of conventional
digital system design
Diode load and Resistive load designs have
High static power consumption
Poor noise margin
Lager gain lower noise margin so cascading of
diode load inverters will not work
Complementary type inverters have asymmetric
characteristics due to their mobility
Less reliable and slower than monotype

Introduction
TFTs are key elements for flexible electronics
Monotype TFTs are used
2 categories of TFTs
1.
P type and N type
2.
Single VT and Dual VT
TFT technologies
1. P type SAM OTFTs
2.
N type IGZO TFTs
Transfer printing method

COMPARISON O F VARIOUS TFT TECHNOLOGIES

2-V SAM OTFTs

Drainsource current IDS versus (a) the gate voltage VGS and (b) the
drainsource voltage (VDS ) (W = 500 m,L = 50 m).

Transparent IGZO TFTs

IDS VGS relationship in the log scale for IGZO TFTs on (a) a glass
substrate (VT 23 V) and (b) a polyimide plastic substrate (VT
15 V)

Single and dual Vt

To reduce noise, power, delay problems dual
Vt technology is proposed
Tuning back gate voltage or replacing gate
materials
This increases complexity and requires special
circuitry

COMPARISON OF ORGANIC INVERTERS

Two varieties of Pseudo-CMOS inverter designs. The differences between

Pseudo-E and Pseudo-D inverters are the gate connection of M2 and the
M1/M2 pair channel-width-sizing ratio W1/W2.

Inverter VTCs of the proposed Pseudo-E and Pseudo-D inverters. Each

curve represents VTC under different tuning voltage VSS. The maximal
achievable inverter gain is tunable and can reach >20 for Pseudo-D
inverters

Schematics of Pseudo-E and Pseudo-D NAND gates implemented in ptype TFTs.

Pseudo-D NAND transfer function by fixing one input and varying the
other input. (a) When input B is kept high and (b) when input A is kept
high. The nearly identical curves reveal a good input symmetry of the
NAND gate.

Schematics of Pseudo-E and Pseudo-D inverters in n-type TFTs. ( =

(W1 /W2 ) (1/2) and = (W3 /W4 ) (2/1) are used in the test case on
both glass and plastic samples. Both MUN and MDN use the same
minimum channel width.)

Pseudo D Inverter
Most robust
Transistor sizing
Post fabrication tuning
When Vss tuned from 40 to 60V
Output high 19.87->33.04
Gain 1.87->3.4

Inverter VTCs and gain plots of a Pseudo-D inverter with different VSS
voltages. All inverters are implemented in n-type IGZO TFTs on a
polyimide substrate. (VDD = 40 V, and = 1).

Advantages
Requires only monotype single Vt TFTs
Built in post fabrication tunability
Applicable to either enhanced or depletion mode
TFTs
Operating voltage<=2V
Reliability

Disadvantages

Complex material treatment

Complex process Integration

High manufacturing cost if making

complementary type TFT circuits

Applications

Sensors

Displays

Low cost RF identification (RFID) tags, etc