Design and Modeling of

Combinational Logic Circuits

Analysis Procedure, Design Procedure

Binary Adder- Subtractor,
Parallel Adder, Carry look Ahead Adder,
Binary Multiplier,
Code Converters-Binary to Gray, Gray to Binary, BCD toExcess-3 Code
Conversion and vice versa, BCD to 7-segment code converter,

Magnitude Comparator 4 bit, Decoders, Encoders,

Multiplexers, De-multiplexer,
Parity generator and checker.

Modeling of above combinational circuits

using Verilog

The Gray Code

The Gray code is unweighted and is
not an arithmetic code.
There are no specific weights assigned
to the bit positions.

Important: the Gray code exhibits

only a single bit change from one
code word to the next in sequence.
This property is important in many
applications, such as shaft position
encoders.

The Gray Code

Decim
al
0
1
2
3
4
5
6
7

Binar
y
0000
0001
0010
0011
0100
0101
0110
0111

Gray
Code
0000
0001
0011
0010
0110
0111
0101
0100

Decim
al
8
9
10
11
12
13
14
15

Binar
y
1000
1001
1010
1011
1100
1101
1110
1111

Gray
Code
1100
1101
1111
1110
1010
1011
1001
1000

The Gray Code

Binary-to-Gray code conversion
The MSB in the Gray code is the same as
corresponding MSB in the binary
number.
Going from left to right, add each
adjacent pair of binary code bits to get
the next Gray code bit. Discard carries.
ex: convert 101102toGraycode
1+0+1+1+0binary
11101Gray

The Gray Code

Gray-to-Binary Conversion
The MSB in the binary code is the same as
the corresponding bit in the Gray code.
Add each binary code bit generated to the
Gray code bit in the next adjacent position.
Discard carries.
ex: convert the Gray code word 11011to
binary
11011Gray
++++
10010Binary

The Gray Code - Application

Bit0
Bit1
Bit2
Bit3

http://www.mipraso.de/enzyk
lopaedie/g/gray-codescheibe.gif

http://www.engr.colostate
.edu/~dga/mechatronics/
figures/9-11.gif

BCD-to-Excess-3 Code
converter
BCD is a code for the decimal digits
0-9
Excess-3 is also a code for the
decimal digits

9/15/09 - L12 Combinational

Logic Design

Copyright 2009 - Joanne DeGroat,

ECE, OSU

10

Specification of BCD-toExcess3
Inputs: a BCD input, A,B,C,D with A
as the most significant bit and D as
the least significant bit.
Outputs: an Excess-3 output W,X,Y,Z
that corresponds to the BCD input.
Internal operation circuit to do the
conversion in combinational logic.

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Formulation of BCD-toExcess-3
Excess-3 code is easily formed by
adding a binary 3 to the binary or
BCD for the digit.
There are 16 possible inputs for both
BCD and Excess-3.
It can be assumed that only valid
BCD inputs will appear so the six
combinations not used can be
treated as dont cares.
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Optimization BCD-toExcess-3
Lay out K-maps for each output, W X
YZ

A step in the digital circuit design

process.
13

Placing 1 on K-maps
Where are the minterms located on a
K-Map?

14

Expressions for W X Y Z
W(A,B,C,D) = m(5,6,7,8,9)
+d(10,11,12,13,14,15)
X(A,B,C,D) = m(1,2,3,4,9)
+d(10,11,12,13,14,15)
Y(A,B,C,D) = m(0,3,4,7,8)
+d(10,11,12,13,14,15)
Z(A,B,C,D) = m(0,2,4,6,8)
+d(10,11,12,13,14,15)
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Minimize K-Maps
W minimization

Find

W = A + BC + BD

16

Minimize K-Maps
X minimization

Find

X = BCD+BC+BD

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Minimize K-Maps
Y minimization

Find

Y = CD + CD

18

Minimize K-Maps
Z minimization

Find

Z = D

19

Two level circuit

implementation
Have equations

W = A + BC + BD = A + B(C+D)
X = BC + BD + BCD = B(C+D) + BCD
Y = CD + CD
Z = D

Factoring out (C+D) and call it T

Then T = (C+D) = CD

W = A + BT
X = BT + BT
Y = CD + T
Z = D

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Create the digital circuit

Implementing
the second
set of
equations
where
T=C+D
results in a
lower gate
count.
This gate has

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BCD-to-Seven-Segment
Decoder
Specification
Digital readouts on many digital
products often use LED seven-segment
displays.
Each digit is created by lighting the
appropriate segments. The segments
are labeled a,b,c,d,e,f,g
The decoder takes a BCD input and
outputs the correct code for the sevensegment display.
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Specification
Input: A 4-bit binary value that is a
BCD coded input.
Outputs: 7 bits, a through g for each
of the segments of the display.
Operation: Decode the input to
activate the correct segments.

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Formulation
Construct a truth table

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Optimization
Create a K-map for each output and
get
A = AC+ABD+BCD+ABC
B = AB+ACD+ACD+ABC
C = AB+AD+BCD+ABC
D = ACD+ABC+BCD+ABC+ABCD
E = ACD+BCD
F = ABC+ACD+ABD+ABC
G = ACD+ABC+ABC+ABC
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Note on implementation
Direct implementation would require
27 AND gates and 7 OR gates.
By sharing terms, can actualize and
implementation with 14 less gates.
Normally decoder in a device name
indicates that the number of outputs
is less than the number of inputs.
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