A FPGA Implementation of High

Security Hybrid Reconfigurable

Cryptographic Processor with RSA
and SEA

PRESENTATION ORAGANISATION
MOTIVATION
PROPOSED SYSTEM
HYBRID RTL SCHEMATIC DIAGRAM
RSA ALGORITHM
SEA ALGORITHM
SIMULATION RESULTS
CONCLUSION AND FUTURE WORK
REFERENCES

MOTIVATION
Today more and more sensitive data is stored digitally. Military
data , Bank accounts, medical records and personal emails are
some categories where datas must be secure.
The use of systems with increasing complexity, which usually
are more secure has a low throughput rate and more energy
consumption.
Protecting the digital data through encryption using tools and
external codes are highly cost effective and also results in
performance degradation.

 To achieve much efficiency in encryption a reconfigurable

cryptographic microprocessor is designed in this project which
offer maximum digital security.
Till

now

either

symmetric

cryptographic

processor

or

asymmetric cryptographic processor is implemented, but not

both together.
This

leads

to

the

basis

for

this

project

to

exploit

the

advantages of both symmetric and asymmetric cryptographic

processor.
We are implementing both the algorithms together as Hybrid
which offers double security

PROPOSED SYSTEM

In this project we are proposing a Hybrid architecture in

which the advantages of both asymmetric and symmetric
cryptographies are combined.

For implementation, an Asymmetric RSA (Rivest-ShamirAdelman) cryptography and a symmetric light weight SEA
(Scalable

Encryption

Algorithm)

cryptography

are

combined to mutate a reconfigurable instruction driven

cryptographic processor.

COMPARISON BETWEEN RSA AND

SEA
Feature

RSA

SEA

Encryption and Decryption

Asymmetric

Symmetric

Key used

Public key

Secret key

Type

Stream cipher

Block cipher

Security

High

Low

Speed

Low

High

Scalability

No

Yes

Power and Area

More

Less

Ciphering & deciphering key

different

Same

Operations used in algorithm

Modular Arithmetic

Logical, Rotation and

Shifting operations

Cryptanalysis method

product factorization

no known method

PROPOSED ARCHITECTURE
HYBRID

RW

RSA
Enc
Data IN

Random
Logic
Selection

En

KEY RSA

Data
Mux 1

HYBRID DOUT

SEA
Enc

Address

RSA Dout

SEA Dout
KEY SEA

Key
Mux 2
En

KEY HYBRID

HYBRID

RSA
Dec

Data OUT

Mux 3
SEA
Dec

RW
Enc Data
Memory
Address
Key
Address
En

Look Up
Table

RTL SCHEMATIC OF HYBRID

SYSTEM

HARDWARE DESCRIPTION
Controller Unit

32
Reconfigurable
Cryptographic
Unit

Random Logic
and selection
Unit

Length & Shut

Down Controller

Data and Key

Mux

Memory
Cell

Instruction
LUT

I/O interface
Registers
Internal Bus
System Bus
32

RSA ALGORITHM
P&Q (Two large prime numbers are
choiced)

N=P*Q

Public key: E & private key: D

Encryption CT=PTe mod n.

CT to receiver

Decryption PT= CTd mod n.

RSA ALGORITHM EXAMPLE

Select the prime integers q=11, q=3.
n=pq=33; (n)=(p-1)(q-1)=20
Choose e=3

Check gcd(3,20)=1

Compute d=7

(3)d 1 (mod 20)

Therefore the public key is (n, e) = (33, 3) and the private key is (n, d) = (33, 7).
Now say we wanted to encrypt the message M=7
C = Me mod n
C = 73 mod 33
C = 343 mod 33
C = 13
So now the cyphertext C has been found. The decryption of C is performed as
follows.
M' = Cd mod n
M' = 137 mod 33
M' = 62,748,517 mod 33
M' = 7

RSA RESULT ANALYSIS

RSA Mapping

RSA Timing Analysis

Total Logic Elements

56

Frequency

177 MHZ

Dedicated Logic Registers

38

Worst case tco

8.410 ns

Combinational functions

56

Clock set up

5.649 ns

Total pins

17

RSA Power Analysis

Total Power Dissipation

68.55 mW

Core static Power Dissipation

47.25mW

I/O thermal power

dissipation

21.20mW

SEA ALGORITHM

SEA RESULT ANALYSIS

SEA Timing Analysis

SEA Mapping
Combinational
ALUTs

368

Frequency

330.17 MHZ

Total pins

240

Worst case tsu

6.091 ns

Worst case tco

15.969 ns

Worst case tpd

9.333ns

Worst case th

2.636 ns

Clock set up

2.945 ns

SEA Power Analysis

Total Thermal
power dissipation

322.2
mW

Core Static power

dissipation

303.05
mW

I/O thermal power

dissipation

27.80
mW

HYBRID PROCESSOR WITH RSA AND SEA

RESULT ANALYSIS
Hybrid Mapping
Hybrid Timing
Total Logic Elements
702
Analysis
Dedicated Logic Registers
Combinational functions
Total pins

353
88.97 MHZ

Worst case tsu

7.98 ns

Worst case tco

15.12 ns

Worst case tpd

9.271ns

Worst case th

2.636 ns

Clock set up

11.240 ns

701
99

Hybrid Power Analysis

Total Thermal
power dissipation

Frequency

78.05
mW

Core Static power

dissipation

47.37m
W

I/O thermal power

dissipation

31.19
mW

SIMLULATION RESULT OF RSA

SIMULATION RESULT OF SEA

SIMULATION RESULT OF HYBRID PROCSSOR

CONCLUSION AND FUTURE WORK

Thus the proposed Hybrid cryptographic processor using RSA
and SEA has the greater advantage of double security. By
using the shut down controller much power can be reduced.

Multi pipelined architecture can be implemented in future

work to increase the speed and to reduce the computational
time.

REFERENCES
[1]. Jun-Hong Chen, Ming-Der Shieh, Member, IEEE, and Wen-Ching Lin (2010). A HighPerformance Unified-Field Reconfigurable Cryptographic Processor in the proceedings of
IEEE transactions on very large scale integration (vlsi) systems, vol. 18, no. 8.
[2]. Neil Smyth, Mire McLoone and John V McCanny (2005). Reconfigurable Processor for
Public-Key Cryptography in the proceedings of IEEE.
[3]. Qiang Liu Fangzhen Dong Tong Xu Cheng. (2004). A Regular Parallel RSA Processor in
the proceedings of the 47rh IEEE International Midwest Symposium on Circuits and Systems
in the proceedings of IEEE
[4]. Jun-Hong Chen, Ming-Der Shieh, Member, IEEE, and Wen-Ching Lin (2010). A HighPerformance Unified-Field Reconfigurable Cryptographic Processor in the proceedings of
IEEE transactions on very large scale integration (vlsi) systems, vol. 18, no. 8.

[5]. Goodman J and A. P. Chandrakasan, (2001) An energy-efficient

reconfigurable public-key cryptography processor, in the proceedings of
IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 18081820.
[6]. Yang Qian, Wu Xingiun, Zhou Runde, Lu Ruibing (2008) An
Embedded

RSA

processor

for

encryption

and

Decryptio

in

the

proceedings of IEEE., 1-9.

[7].X. Zeng, C. Chen, and Q. Zhang, (2004) A reconfigurable public-key
cryptography coprocessor in Proc. IEEE Asia Pacific Conf. Adv. Syst.
Integr. Circuits, pp. 172175.
[8].Zhu Kejia , Xu Ke, Wang Yang, and Min Hao (2009) A Novel ASIC
Implementation of RSA Algorithm ,in the proceedings of IEEE.
[9].N. Smyth, M. McLoone, and J. V. McCanny, (2006) An adaptable and
scalable asymmetric cryptographic processor, in Proc. IEEE Int. Conf.
Appl.-Specific Syst. Arch. Processors, pp. 341346.

THANK YOU