Microprocessors:: General-Purpose Microprocessor

Microprocessors:
General-purpose microprocessor
CPU for Computers

No RAM, ROM, I/O on CPU chip itself
Example Intels x86, Motorolas 680x0
CPU
GeneralPurpose
Microprocessor
Many chips on mothers board
Data Bus
RAM
ROM
I/O
Port
Address Bus
General-Purpose Microprocessor System
Timer
Serial
COM
Port
Microcontroller :
A smaller computer
On-chip RAM, ROM, I/O ports...
Example Motorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X
CPU
I/O
Port
RAM ROM
Serial
Timer COM
Port
A single chip
Microcontroller
Microprocessor vs. Microcontroller

Microcontroller
Microprocessor
CPU, RAM, ROM, I/O and
CPU is stand-alone, RAM,
timer are all on a single chip
ROM, I/O, timer are separate fix amount of on-chip ROM,
designer can decide on the
RAM, I/O ports
amount of ROM, RAM and
for applications in which cost,
I/O ports.
power and space are critical
expansive
single-purpose
versatility
general-purpose
Block Diagram
External interrupts
Interrupt
Control
On-chip
ROM for
program
code
Timer/Counter
On-chip
RAM
Timer 1
Timer 0
CPU
OSC
Bus
Control
4 I/O Ports
P0 P1 P2 P3
Address/Data
Serial
Port
TxD RxD
Counter
Inputs
Pin Description of the 8051

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
(T0)P3.4
(T1)P3.5
(WR)P3.6
(RD)P3.7
XTAL2
XTAL1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
8051
(8031)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Vcc
P0.0(AD0
P
) 0.1(AD1)
P0.2(AD2
P
) 0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14
)P2.5(A13
P
) 2.4(A12
)P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
Figure (b). Power-On RESET Circuit

Vcc
+
10 uF
31
30 pF
8.2 K
30 pF
11.0592 MHz
19
18
EA/VPP
X1
X2
9 RST
Registers
A
B
R0
DPTR
DPH
DPL
R1
R2
PC
PC
R3
R4
R5
R6
R7
Some 8-bitt Registers of
the 8051
Some 8051 16-bit Register
Addressing Modes
Addressing modes specifies where

the data (operand) is. They specify
the source or destination of data
(operand) in several different ways,
depending upon the situation.
Addressing modes are used to know

where the operand located is.
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Addressing Modes
1.
2.
3.
4.
5.
There are 5 types of addressing

modes:
Register addressing.
Direct addressing.
Register indirect addressing.
Immediate addressing.
Index addressing.
Register Addressing Mode
In register addressing mode; the

source and/or destination is a
register.
In this case; data is placed in any of

the 8 registers(R0-R7); in
instructions it is specified with letter
Rn (where N indicates 0 to 7).
Register Addressing Mode
1.
2.
For example;
ADD A, Rn (This is general
instruction).
ADD A, R5 (This instruction will
add the contents of register R5
with the accumulator contents).
Direct Addressing Mode
In direct addressing mode; the

address of memory location
containing data to be read is
specified in instruction.
In this case; address of the data is

given with the instruction itself.
Direct Addressing Mode
1.
For example;
MOV A, 25H (This instruction will
read/move the data from internal
RAM address 25H and store it in
the accumulator.
Register Indirect
Addressing Mode
In register indirect addressing mode;

the contents of the designated register
are used as a pointer to memory.
In this case; data is placed in memory,

but address of memory location is not
given directly with instruction.
Register Indirect
Addressing Mode
1.
For example;
MOV A,@R0 This instruction
moves the data from the register
whose address is in the R0
register into the accumulator.
Immediate Addressing
Mode
In immediate addressing mode, the

data is given with the instruction
itself.
In this case; the data to be stored in

memory immediately follows the
opcode.
Immediate Addressing
Mode
1.
For example;
MOV A, #25H (This instruction will

move the data 25H to
accumulator.
Index Addressing Mode
Offset (from accumulator) is added to the

base index register( DPTR OR Program
Counter) to form the effective address of
the memory location.
In this case; this mode is made for

reading tables in the program memory.
Index Addressing Mode
1.
For example;
MOVC A, @ A + DPTR ( This
instruction moves the data from
the memory to accumulator;
whose address is computed by
adding the contents of
accumulator and DPTR)
Types Of Instructions
1.
2.
3.
4.
5.
Data transfer instructions.

Arithmetic instructions.
Logical instructions.
Logical instructions with bits.
Branch instructions.
Data Transfer Instructions
These instructions move the content

of one register to another one.
Data can be transferred to stack

with the help of PUSH and POP
instructions.
MNEMONIC
BYTES
DESCRIPTION
MOV A,Rn
(A)
(Rn)
MOV A,Rx
(A)
(Rx)
MOV A,@Ri
(A)
(Ri)
MOV A,#X
(A)
Data
MOV Rn,A
(Rn)
(A)
MOV Rn, Rx
(Rn)
(Rx)
MOV Rn, #X
(Rn)
Data
MOV Rx, A
(Rx)
(A)
MOV Rx, Rn
(Rx)
(Rn)
MOV Rx, Ry
(RX)
MOV Rx, @ Ri
(Rx)
MOV Rx, # X
(Rx)
(Ry)
(Ri)
Data
MOV @ Ri, A
(Ri)
(A)
MOV @ Ri, Rx
(Ri)
(Rx)
MOV @ Ri, #X
(Ri)
Data
XCH A, Rn
(A)
(Rn)
XCH A, Rx
(A)
(Rx)
XCH A, @Ri
(A)
(Ri)
Arithmetic Instructions
These instructions perform several

basic operations. After execution, the
result is stored in the first operand.
8 bit addition, subtraction,

multiplication, increment-decrement
instructions can be performed.
MNEMONICS
BYTE
ADD A, Rn
A = A + Rn
ADD A, Rx
A = A + Rx
AAD A, @ Ri
A = A+ Ri
DESCRIPTION
ADD A, # X
A = A + Byte
ADDC A, Rn
A = A + Rn + C
ADDC A , Rx
A = A + Rx + C
ADDC A, @ Ri
ADDC A, # X
SUBB A, Rn
A = A + Ri + C
A = A + Byte + C
A = A Rn 1
SUBB A, Rx
A = A Rx 1
SUBB A, @ Ri
A = A Ri 1
SUBB A, # X
A = A Byte 1
INC A
A=A+1
INC Rn
Rn = Rn + 1
INC Rx
Rx = Rx + 1
INC @ Ri
Ri = Ri + 1
DEC A
A=A1
DEC Rn
Rn = Rn 1
DEC Rx
Rx = Rx 1
DEC @ Ri
Ri = Ri 1
INC DPTR
DPTR = DPTR + 1
MUL AB
B:A = A * B
DIV AB
A = [A/B]
DA A
Decimal adjustment of
accumulator according to BCD
code
Logical Instructions
These instructions perform logical

operations between two register
contents on bit by bit basis.
After execution, the result is stored

in the first operand.
MNEMONIC
BYTE
ANL A, Rn
(A)
(A) ^ (Rn)
ANL A, Rx
(A)
(A) ^ (Rx)
ANL A,@ Ri
(A)
(A) ^ (Ri)
DESCRIPTION
ANL A, # X
(A) (8 bit data) ^ (A)
ANL Rx, A
(Rx)
ANL Rx,# X
(Rx)
(Rx) (8 bit data) ^
(A) ^ (Rx)
ORL A, Rn
(A)
(A) + (Rn)
ORL A, Rx
(A)
(A) + (Rx)
ORL A, @ Ri
(A)
(A) + (Ri)
ORL Rx, A
(Rx) (A) + (Rx)
ORL Rx,# X
(Rx)
(Rx) (8 bit data) +
XORL A, Rn
Logical exclusive
OR operation between the contents
of accumulator and R register.
XORL A, Rx
Logical exclusive OR
operation between the contents of the
accumulator and directly addressed
register Rx.
XORL A,@ Ri
operation between
the contents of the accumulator and
directly addressed register.
XORL A, # X
operation between the
contents of accumulator and the given
8 bit data.
XORL Rx, A
operation between the
contents of the accumulator and
directly addressed register Rx.
XORL Rx, # X
operation between the contents of the
directly addressed register Rx and the
given 8 bit data.
CLR A
(A)
0
CPL A
(A)
(/A)
SWAP A
RL A
RLC
(A3-0)
(A7-4)
(An + 1)
(A0)
(An + 1)
(A0)
(C)
(An)
(A7)
(An)
(C)
(A7)
RR A
(An)
(An + 1)
(A7)
RRC A
(An)
(A0)
(An + 1)
(A7)
(C)
(C)
(A0)
Logical Instructions On
Bits
Similar to logical instructions,

these instructions also perform
logical operations.
The difference is that these

operations are performed on single
bits.
Bits
MNEMONIC
BYTE
CLR C
CLR bit
bit
SETB C
DESCRIPTION
(C=0)
clear directly addressed
(C=1)
Bits
SETB bit
Set directly
addressed bit
CPL C
(1 = 0, 0 = 1)
CPL bit
directly
Complement
addressed bit
Bits
ANL C, bit
Logical AND
operation
between Carry bit
and directly addressed bit.
ANL C,/bit
Logical AND
operation
between Carry bit
and inverted directly addressed bit.
Bits
ORL C, bit
Logical OR
operation
2 between Carry bit
and directly addressed
bit.
ORL C,/bit
Logical OR
operation
2 between Carry bit
and inverted directly addressed bit.
Bits
MOV C, bit
addressed 2
Move directly
bit to carry bit.
MOV bit, C
Move Carry bit to
directly 2 addressed bit.
Program Flow Control

Instructions
In this group, instructions are related

to the flow of the program, these are
used to control the operation like,
JUMP and CALL instructions.
Some instructions are used to

introduce delay in the program, to
the halt program.

Instructions
MNEMONIC
ACALL adr11
DESCRIPTION
(PC)
(PC) + 2
(SP)
(SP) + 1
((SP))
(PC7 0)
(SP)
(SP) + 1
((SP))
(PC15-8)
BYTE
2

Instructions
RET
(PC15-8)
(SP)
(PC7-0)
(SP)
1
((SP))
(SP) 1
((SP))
(SP) -

Instructions
RET1
AJMP addr11
(PC15-8)
((SP))
(SP)
(SP) 1
(PC7-0)
((SP))
(SP)
(SP)
(PC)
(PC10-0)
(PC) + 2
page address

Instructions
LJMP addr16
SJMP rel
(PC)
addr15-0
short jump from

(from -128 to +127 locations in
relation to first next
instruction)

Instructions
JC rel
(PC)
(PC) + 2
IF ( C ) = 1
THEN (PC)
(PC) + rel
JNC rel
(PC)
(PC) + 2
IF ( C) = 0
THEN (PC)
(PC) + rel

Instructions
JB bit, rel
Jump if addressed
bit is set. Short jump.
JBC bit, rel
Jump if addressed
bit is set and clear it.

Instructions
JMP @A + DPTR (PC)
JZ rel
(PC)
(A) + (DPTR)
(PC) + 2
IF (A) = 0
THEN (PC) (PC) + rel

Instructions
JNZ rel
(PC)
(PC) + 2
IF (A) = 0
THEN (PC)
(PC) + rel
CJNE A, Rx, rel

Compare the contents
of acc. And directly addressed register
Rx. Jump if they are different. Short jump.
SFR Special Function

Register
There are many special functions registers in

the 8051. We call them SFR.
Example A, B, PSW, and DPTR
The 8051 Assembler provides that the SFR can
be accessed by their name or by their
addresses.
See Table 5-1 for SFR addresses
The SFR have addresses between 80H and FFH.
Not all the address space of 80 to FF is used by
the SFR.
62
Table 5-1: Special Function

Register
Symbol
Name(SFR)
Address
ACC*
Accumulator
Addresses
1/2 0E0H
B*
B register
0F0H
PSW*
Program status word
0D0H
SP
Stack pointer
81H
DOTR
Data pointer 2 bytes
DPL
Low byte
82H
DPH
High byte
83H
P0*
Port 0
80H
P1*
Port 1
90H
P2*
Port 2
0A0H
P3*
Port 3
0B0H
IP*
Interrupt priority control
0B8H
IE*
Interrupt enable control
0A8H
63
Table 5-1: Special Function

Register
Symbol
Name(SFR) Addresses
Address
TCON*
Timer/counter control
88H
2/2
T2CON*
Timer/counter 2 control
0C8H
T2MOD
Timer/counter mode control
0C9H
TH0
Timer/counter 0 high byte
8CH
TL0
Timer/counter 0 low byte
8AH
TH1
8DH
TL1
8BH
TH2
0CDH
TL2
0CCH
RCAP2H
T/C 2 capture register high byte
0CBH
RCAP2L
T/C 2 capture register low byte
0CAH
SCON*
Serial control
98H
SBUF
Serial data buffer
99H
64
Example 5-1
Write code to send 55H to ports P1 and P2, using
(a) their names
(b) their addresses.
Solution:
(a) MOV A,#55H
;A=55H
MOV P1,A
;P1=55H
MOV P2,A
;P2=55H
(b)
From Table 5-1, P1 address = 80H; P2

address = A0H
MOV A,#55H
;A=55H
MOV 80H,A
;P1=55H
MOV 0A0H,A
;P2=55H
65

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Microprocessors:

CPU for Computers

Many chips on mothers board

Microprocessor vs. Microcontroller

Pin Description of the 8051

Figure (b). Power-On RESET Circuit

Some 8051 16-bit Register

Addressing modes specifies where

Addressing modes are used to know

There are 5 types of addressing

Register Addressing Mode

In register addressing mode; the

In this case; data is placed in any of

Register Addressing Mode

Direct Addressing Mode

In direct addressing mode; the

In this case; address of the data is

Direct Addressing Mode

In register indirect addressing mode;

In this case; data is placed in memory,

In immediate addressing mode, the

In this case; the data to be stored in

MOV A, #25H (This instruction will

Index Addressing Mode

Offset (from accumulator) is added to the

In this case; this mode is made for

Index Addressing Mode

Data transfer instructions.

Data Transfer Instructions

These instructions move the content

Data can be transferred to stack

Data Transfer Instructions

Data Transfer Instructions

Data Transfer Instructions

Data Transfer Instructions

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Data Transfer Instructions

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Data Transfer Instructions

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These instructions perform several

8 bit addition, subtraction,

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These instructions perform logical

After execution, the result is stored

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(A) (8 bit data) ^ (A)

(Rx) (8 bit data) ^

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(Rx) (A) + (Rx)

(Rx) (8 bit data) +

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Similar to logical instructions,

The difference is that these

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