MULTILEVEL INVERTERS

Dr. Venkata Reddy Kota

Assistant Professor
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
JNTU KAKINADA

INTRODUCTION
A multilevel converter has several advantages over a conventional two-level converter and can be briefly
summarized as follows.

Staircase waveform quality: Generates output voltages with very low distortion and reduce dv/dt
stresses; therefore electromagnetic compatibility (EMC) problems can be reduced.

Common-mode (CM) voltage: Multilevel converters produce smaller CM voltage; therefore, the
stress in the bearings of a motor connected to a multilevel motor drive can be reduced.

Input current: Multilevel converters can draw input current with low distortion.

Switching frequency: Multilevel converters can operate at both fundamental switching frequency
and high switching frequency PWM. It should be noted that lower switching frequency usually
means lower switching loss and higher efficiency.

Disadvantages:

Greater number of power semiconductor switches are needed.

Although lower voltage rated switches can be utilized in a multilevel converter, each switch requires
a related gate drive circuit. This may cause the overall system to be more expensive and complex.

Applications of multilevel converter

Industrial Medium-Voltage Motor Drives, Utility Interface for Renewable Energy Systems,
Flexible AC Transmission System (FACTS) and Traction Drive Systems, etc,.
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MULTILEVEL INVERTERS

Three different major multilevel converter structures are

1)

Diode Clamped (Neutral Point Clamped),

2)

Flying Capacitors (Capacitor Clamped), and

3)

Cascaded H-Bridges converter with separate dc sources

1)

DIODE CLAMPED MULTILEVEL INVERTER:

a)

The main concept of this inverter is to use diodes to limit the power devices voltage stress.

b)

The voltage over each capacitor and each switch is Vdc .

c)

An m level inverter needs (m-1) voltage sources, 2(m-1) switching devices and (m-1) (m-2)
diodes.
e.g.: In a 3-level Diode Clamped Multilevel: m=3, Therefore:
Number of switches per leg =2(3-1) =4
Number of diodes per leg = (3-1) (3-2) =2
Number of DC capacitors = (3-1) =2

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THREE LEVEL DIODE CLAMPED MLI

Sw1a

Sw2a

Sw3a

Sw1b

Sw2b

Sw1c

Sw2c

Sw3c

Sw1d

Sw2d

Sw3d

Sw3b

Fig1: Three Phase Three Level Diode Clamped Inverter Topology

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Contd
Table 1: Switching States Three Level DCMLI For Output Voltages

Switching States

Power Device
Index

Sw1a

Sw1b

Sw1c

Sw1d

Vdc/2

-Vdc/2

Three Level single leg output voltage

200

V o lt a g e (V o lt s )

150
100
50
0
-50
-100
-150
-200

0.01

0.02

0.03

0.04

0.05
Time (sec)

0.06

0.07

0.08

0.09

0.1

Fig 2: Single Leg Output Voltage of Three Level Diode Clamped Inverter

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FIVE LEVEL DIODE CLAMPED MLI

300 V

Fig1: Three Phase Five Level Diode Clamped Inverter Topology

Contd
Table 1: Switching States Five Level DCMLI For Output Voltages

Switching States

Voltage
Va

Vdc/2
Vdc/4
0
-Vdc/4
-Vdc/2

Sw1a

Sw1b

Sw1c

Sw1d

S1w1a

S1w1b

S1w1c

S1w1d

0
0
0

1
0
0

1
1
0

1
1
1

1
1
1

0
1
1

0
0
1

0
0
0

Five Level Single Leg DC MLI

150
100

Voltage (volts)

50
0
-50

-100
-150
0

0.01

0.02

0.03

0.04

0.05
Time (sec)

0.06

0.07

0.08

0.09

0.1

Fig 2: Single Leg Output Voltage of Three Level Diode Clamped Inverter

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Contd
Applications of Diode-clamped Inverter:
1.

an interface between a high-voltage dc transmission line and an ac transmission line.

2.

In variable speed drives for high-power medium-voltage (2.4 kV to 13.8 kV) motors.

3.

Static var compensation

Advantages:
1)

All of the phases share a common dc bus, which minimizes the capacitance requirements of the
converter. For this reason, a back-to-back topology is possible such as in a high-voltage back-toback inter-connection or an adjustable speed drive.

2)

The capacitors can be pre-charged as a group.

3)

Efficiency is high for fundamental frequency switching.

Disadvantages:
1)

Real power flow is difficult for a single inverter because the intermediate dc levels will tend to
overcharge or discharge without precise monitoring and control.

2)

The number of clamping diodes required is quadratically related to the number of levels, which can
be cumbersome for units with a high number of levels.

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Contd
2) CAPACITOR CLAMPED MULTILEVEL INVERTER:
1)

Maynard and Foch introduced a flying-capacitor-based inverter in 1992.

2)

The structure of this inverter is similar to that of the diode-clamped inverter except that instead of
using clamping diodes, the inverter uses capacitors in their place.

3)

Unlike the diode-clamped inverter, the flying-capacitor inverter does not require all of the switches
that are on (conducting) be in a consecutive series.

4)

The flying-capacitor inverter has phase redundancies, whereas the diode-clamped inverter has only
line-line redundancies. These redundancies allow a choice of charging/discharging specific
capacitors and can be incorporated in the control system for balancing the voltages across the
various levels.

5)

An m level inverter needs (m-1) voltage sources, 2(m-1) switching devices and (m-1) (m-2)/2
auxiliary capacitors.
e.g.: In a 3-level Capacitor Clamped Multilevel: m=3, Therefore:
Number of switches per leg =2(3-1) =4
Number of auxiliary capacitor per leg = (3-1) (3-2)/2 =1
Number of DC Capacitors = (3-1) =2

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THREE LEVEL CAPACITOR CLAMPED MLI

Sw1a

Sw2a

Sw3a

Sw2c

E
C

3
g

[L3c]

Sw3c
m

Sw1c

1
2

[L2c]

C4

Sw3b
m

C7

Sw2b
E

C5

Sw1b

C1

C2
[L2d]

Sw2d
E

Sw3d
m

Sw1d

[L3d]

Fig1: Three Phase Three Level Capacitor Clamped Inverter Topology

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Contd
Table 2: switching states of Three Level FCMLI for output voltages

Switching states

Power
Device Index

Sw1a

Sw1b

Sw1c

Sw1d

VDC/2
0
0
-V DC/2

1
0
1
0

1
1
0
0

0
0
1
1

0
1
0
1

Three Level single leg output voltage

200

V o lt a g e (V o lt s )

150
100
50
0
-50
-100
-150
-200

0.01

0.02

0.03

0.04

0.05
Time (sec)

0.06

0.07

0.08

0.09

0.1

Fig 2: Single Leg Output Voltage of Three Level Capacitor Clamped Inverter

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FIVE LEVEL CAPACITOR CLAMPED MLI

Fig1: Three Phase Five Level Capacitor Clamped Inverter Topology

Contd
Table 1: Switching States Five Level DCMLI For Output Voltages

Switching States

Voltage
Va

Vdc/2
Vdc/4
0
-Vdc/4
-Vdc/2

Sw1a

Sw1b

Sw1c

Sw1d

S1w1a

S1w1b

S1w1c

S1w1d

0
0
0

1
0
0

1
1
0

1
1
1

1
1
1

0
1
1

0
0
1

0
0
0

Five level Single leg output voltage

200
150
100

Voltage (volts)

50
0
-50

-100
-150
-200

0.01

0.02

0.03

0.04

0.05
Time (sec)

0.06

0.07

0.08

0.09

0.1

Fig 2: Single Leg Output Voltage of Five Level Capacitor Clamped Inverter

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Contd
Applications of Flying Capacitor Multilevel Inverter:
Static Var Generation
Advantages :
1)

Phase redundancies are available for balancing the voltage levels of the capacitors.

2)

Real and reactive power flow can be controlled.

3)

The large number of capacitors enables the inverter to ride through short duration outages and deep
voltage sags.

Disadvantages:
1)

Control is complicated to track the voltage levels for all of the capacitors. Also, precharging all of the
capacitors to the same voltage level and start up are complex.

2)

Switching utilization and efficiency are poor for real power transmission.

3)

The large numbers of capacitors are both more expensive and bulky than clamping diodes in multilevel
diode-clamped converters.

4)

Packaging is also more difficult in inverters with a high number of levels.

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Contd
3) CASCADED H-BRIDGE MULTILEVEL INVERTER :
Each separate dc source (SDCS) is connected to a single-phase full-bridge, or H-bridge, inverter.
Each inverter level can generate three different voltage outputs, +V dc, 0, and Vdc by connecting the
dc source to the ac output by different combinations of the four switches, S w1, Sw2, Sw3, and Sw4.
The ac outputs of each of the different full-bridge inverter levels are connected in series such that the
synthesized voltage waveform is the sum of the inverter outputs.
The number of output phase voltage levels m in a cascade inverter is defined by m = 2s+1, where s is
the number of separate dc sources.
Applications of Cascaded H-bridge Multilevel Inverter:
static var generation,
Cascaded inverters are ideal for connecting renewable energy sources with an ac grid, because of the
need for separate dc sources, which is the case in applications such as photo voltaic or fuel cells.
Main traction drive in electric vehicles, where several batteries or ultra capacitors are well suited to
serve as SDCSs.
The cascaded inverter could also serve as a rectifier/charger for the batteries of an electric vehicle
while the vehicle was connected to an ac supply. Additionally, the cascade inverter can act as a
rectifier in a vehicle that uses regenerative braking.
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THREE LEVEL CASCADED H-BRIDGE MLI

SW5

SW6

SW9

SW12

E
Iabc

Scope

SW11
m

SW8
m

SW7

SW4

Vabc

SW3

V3

V2

V1

SW10

SW2

SW1

A
B
V

Fig1: Three Phase Three Level Capacitor Clamped Inverter Topology

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Contd
Table 2: switching states of Three Level FCMLI for output voltages

Switching States

Power Device
Index

Sw1

Sw2

Sw3

Sw4

+VDC

0
-VDC

CHB Single Leg Output Voltage

300

V o lt a g e ( v o lt s )

200
100
0
-100
-200
-300
0

0.01

0.02

0.03

0.04

0.05
Time (sec)

0.06

0.07

0.08

0.09

0.1

Fig 2: Single Leg Output Voltage of Three Level Capacitor Clamped Inverter

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FIVE LEVEL CASCADED H-BRIDGE MLI

Fig1: Three Phase Five Level Cascaded H-Bridge Inverter Topology

Contd
Table 2: switching states of Three Level FCMLI for output voltages

Van

Van1
0
V
V
V
0
-V
0
-V
-V

V
2V

-V
-2V

Van2
V
0
V
-V
0
V
-V
0
-V

Van = Van1 +Van2

Five Level single leg voltage

300
200

Voltage (volts)

100
0

-100
-200
-300
0

0.01

0.02

0.03

0.04

0.05
Time(sec)

0.06

0.07

0.08

0.09

0.1

Fig 2: Single Leg Output Voltage of Three Level Capacitor Clamped Inverter

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Contd
Advantages of CHB:

The number of possible output voltage levels is more than twice the number of dc sources
(m = 2s + 1).

The series of H-bridges makes for modularized layout and packaging. This will enable the
manufacturing process to be done more quickly and cheaply.

Disadvantages of CHB:

Separate dc sources are required for each of the H-bridges. This will limit its application to products
that already have multiple SDCSs readily available.
Table 1: Comparison of the components of conventional topologies

Converter type

Diode-clamped Flying capacitors

Cascaded
H-Bridge

Main switching devices

(m-1) x 2

(m-1) x 2

(m-1) x 2

Main diodes

(m-1) x 2

(m-1) x 2

(m-1) x 2

Clamping diodes

(m-1) x (m-2)

Dc bus capacitors

(m-1)

(m-1)

(m-1)/2

(m-1) x (m-2) / 2

Balancing capacitors

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CONTROL STRATEGIES

Abundant modulation techniques and control paradigms have been developed for multilevel converters such as
1)

Sinusoidal Pulse Width Modulation (SPWM),

2)

Selective Harmonic Elimination (SHE-PWM),

3)

Space Vector Modulation (SVM) and others.

The main aim of the modulation strategy of multilevel inverters is to synthesize the output voltage as close as
possible to the sinusoidal waveform.

The natural extensions of carrier based sinusoidal PWM for multilevel converter topologies are
1)

Level-Shift (LSPWM) commonly known as

a)

Phase Disposition (PD), where all carriers are in phase.

b)

Phase Opposition Disposition (POD), where the carriers above the reference zero point are out of
phase with those below the zero point by 180 0.

c)

Alternate Phase Opposition Disposition (APOD), where each carrier is phase shifted by 180' from
its adjacent carriers.

2)

Phase-Shift PWM (PSPWM).

The level-shifted multicarrier modulation technique produces the best harmonic performance, however this
technique produces uneven power distribution among the cells when applied to CHB Multilevel Inverter.

The Phase Shifted Carrier PWM (PSCPWM) is the standard modulation strategy for CHB Multilevel Inverter.
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PHASE DISPOSITION PWM

PHASE DISPOSITION PWM

-2

-4

-6

0.002

0.004

0.006

0.008

0.01
Time

0.012

0.014

0.016

0.018

0.02

0.014

0.016

0.018

0.02

Fig 2: PD PWM for a Three Level Inverter

PHASE DISPOSITION PWM
10
8
6
4
2
0
-2
-4
-6
-8
-10
0

0.002

0.004

0.006

0.008

0.01
Time (sec)

0.012

Fig 2: PD PWM for a Five Level Inverter

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PHASE OPPOSITION DISPOSITION PWM

PHASE OPPOSITION DISPOSITION PWM

-2

-4

-6

0.002

0.004

0.006

0.008

0.01
Time (sec)

0.012

0.014

0.016

0.018

0.02

Fig 2: POD PWM for a Three Level Inverter

PHASE OPPOSITION DISPOSITION PWM
10
8
6
4
2
0
-2
-4
-6
-8
-10
0

0.002

0.004

0.006

0.008

0.01
Time (sec)

0.012

0.014

0.016

0.018

0.02

Fig 2: POD PWM for a Five Level Inverter

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ALTERNATE PHASE DISPOSITION PWM

ALTERNATE PHASE OPPOSITION DISPOSITION PWM

-2

-4

-6

0.002

0.004

0.006

0.008

0.01
Time (sec)

0.012

0.014

0.016

0.018

0.02

Fig 2: APOD PWM for a Three Level Inverter

ALTERNATE PHASE OPPOSITION DISPOSITION PWM
10
8
6
4
2
0
-2
-4
-6
-8
-10
0

0.002

0.004

0.006

0.008

0.01
Time (sec)

0.012

0.014

0.016

0.018

0.02

Fig 2: APOD PWM for a Five Level Inverter

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PHASE SHIFTED PWM

6

-2

-4

-6

0.002

0.004

0.006

0.008

0.01
Time (sec)

0.012

0.014

0.016

0.018

0.02

Fig 2: PS PWM for a Three Level Inverter

6
4
2
0
-2
-4
-6

0.002

0.004

0.006

0.008

0.01
Time (sec)

0.012

Fig 2: PS PWM for a Three Level Inverter

0.014

0.016

0.018

0.02