Intermediate

Low Voltage Power MOSFETs

Renesas Electronics America Inc.

Christopher Lee, PMD & GP Products Group
CHRISTOPHER.LEE@RENESAS.COM

408-649-4703

May 2011

Rev.1.0

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Course Introduction
Purpose
This course provides intermediate knowledge of low voltage Power MOSFETs.

Objective
Learn what a power MOSFET is and how it works.
Understand how to read a MOSFET datasheet.
Understand basic MOSFET characteristics.

Content
35 pages (except exam. Session)
5 questions

Learning Time
40 minutes

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MOSFETs

MOSFETs
Packaging Trends
Characteristics and Datasheet
3

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What is a Power MOSFET?

MOSFET: metaloxidesemiconductor field-effect transistor

MOSFET is a transistor used for amplifying or switching electronic signals
In MOSFETs a voltage on the oxide-insulated GATE [G in the diagram below] induces a
conducting channel between the two other contacts called SOURCE [S] & DRAIN [D].
Gate voltage is denoted Vg
A Power MOSFET can switch and conduct very high power levels, an is useful in power
conversion circuits (i.e. boost voltage, decrease voltage , convert DC to AC, etc.)

ID

G
S

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VG
G
S

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What is a Power MOSFET?

The threshold voltage is the minimum VG at which a conducting channel forms.

For switching applications such as for switching voltage regulators, the V G is

modulated between on (> saturation voltage of the channel) and OFF
For switching applications, this channel between the Drain and Source can be thought
of a resistor (RDSON) that is controlled by the VG in power applications.

ID

G
S

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VG
G
S

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Packaging Trends in LV MOSFETs

MOSFETs
Packaging Trends
Characteristics and Datasheet
6

SMD Packages

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Footprint Compatibility
Bottom Side Cooling

Double-Sided Cooling
IR DirectFET

Bottom

Bottom

Bottom

Renesas

Renesas LFPAK-i

(Hitachi, NXP)

LFPAK-i
DLFPAK-i
DD
D DD DD
DTop
Top

Bottom

Bottom

Bottom

S S S G
S S G

Bottom

WPAK

Solutions from Renesas : (LFPAK/LFPAK-i, WPAK) + WINFET/BEAM MOSFETs

8
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Space Saving Packages

Down sizing
SOP-8

HVSON

-64% (5x6 ->3.3x3.3)

WPAK

mini-HVSON
HWSON3030

[ 5x6 ]

[ 3.3x3.3 ]

[ 5x6 ]

LFPAK

LFPAK-i

Compounded Hi/Lo MOSFETs

-56% (5x6 ->3x4.4)

-50% (5x6x2 ->5x6x1)

WPAK-Dual

Down
sizing

[ 5x6 ]

[ 5x6 ]

[ 5x6 ]

Vcc
Driver /
Controller

[ 3x4.4 ]

Vin
Hi
L Vout

Lo

Integrated Power IC
-44% (8x8 ->6x6)

-29% (5x6x3 ->8x8)

QFN56

Down
sizing
[ 8x8 ]

HWSON3044

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QFN40

[ 6x6 ]

Package Roadmap for High Current Application

10

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Package Resistance
Lower PKG resistance Reduces Conduction loss!
Cu wire

Au wire

Lead Frame Cu Wire

(Source, Gate) Die

Lead Frame Au Wire

(Source, Gate) Die

Die pad (Drain)

Die pad (Drain)

~1.0m

AL ribbon
AL ribbon

~0.5m
Wireless
lead
(Source, Gate) Die

LFPAK
LFPAK-i

Die pad (Drain)Au bump

11

SOP-8

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Die

Die pad (Drain)

SOP-8
WPAK
WPAK-Dual
HWSON3044
HWSON3030

Cu clip
Cu clip

Die

Die pad (Drain)

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HVSON
mini-HVSON
3x3mm

Observed Trend Toward Integration

- Another Solution from Renesas VCIN

Driver

REG5V BOOT GH VIN

UVL REG5V

12Vin

SBD

DISBL

CPU
PWM

3-state
Input

CGND

Overlap
Protect.

VLDRV

VSWH

GL PGND

QFN56

QFN40
Down
sizing

[ 8x8 ]

Controller

Top view

Bottom View

[ 6x6 ]

A System in Package, SiP

12

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Characteristics & Datasheet

MOSFETs
Packaging Trends
Characteristics and Datasheet
13

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MOSFET Characteristics
Break down voltages (VDSS, VGSS)
On Resistance (RDSON)
Switching chacteristics
Gate Charge (QG, QGD)
Capacitances (CISS, COSS, etc)

Avalanche
Body Diode
ASO Area of Safe Operation

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Power MOSFET Absolute Maximum Ratings

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MOSFET Electrical Characteristics

Parameter

Symbol

Value

Unit

Temperature
Dependence

Attention
for Design

Min

Typ

VDSS

60

ID=10mA, VGS=0

IDSS

10

VDS=60V, VGS=0

uA

IGSS

0.1 VGS=20V, VDS=0

High dependence on
temperature, but low loss

uA

Gate Source Cutoff Voltage

VGS(off)

1.0

2.5

VDS=10V, ID=1mA

Forward Transfer Admittance

IYfsI (gm)

55

90

ID=45A, VDS=10V

Protection diode built in products

are from scores of nA to scores
of A. The guarantee is 10uA.
Influence on noise at operating
time of SW and SW time tr and tf

Drain Source on Resistance 1 RDS(on)1

4.3

5.5

ID=45A, VGS=10V

Drain Source on Resistance 2 RDS(on)2

6.0

9.0

ID=45A, VGS=4V

Input Capacitance

CISS

9770

VDS=10V

pF

Output Capacitance

COSS

1340

VGS=0

pF

Reverse Transfer Capacitance CRSS

470

FSW =1MHz

pF

Drain-source
destruction voltage
Zero Gate Voltage
Drain Current
Gate to Source Leak Current

Note: VDS(off) = VTH

16

CISS = CGS + CGD

COSS = CDS + CGD
CRSS = CGD

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Max

Test
Condition

(Ta=25degC)

It is related to on-resistance

S = siemens = 1/
This is the most important
parameter to decide on-loss.
Pay attention to rise in curve
with temperature
There is a VDS dependency here.
Indicate drive loss at operating
time of analog
There is VDS dependency.
Influence on fall time tf at light
load time.
There is VDS dependency.
Influence on SW time tr and tf

: Have positive temperature coefficient.

: Have negative temperature coefficient.

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Important MOSFET Device Design Parameters

MOSFET Resistances
Drain

RWIRE
RGI

VDSS

Gate

RG

RGI

RDS(si)

Body
Diode

Rch

N+

P+
Repi

Epi
Rsub

NN++

Substrate

VGSS

RWIRE

Parasitic NPN
Bipolar Transistor

Structure of N-Channel Trench Cell

RDS(si) = Rch + Repi + Rsub

Source

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Vertical MOSFET Cells

Return

Overall RDS(on) Components

Planar
S

RWIRE
G

N+ (S)

P (CH)
N - (Epi)

N ++(Sub)

Trench
G

Rch

N + (S)

P (CH)

Repi

N - (Epi)

Rsub

N ++(Sub)

Drain of the Si is glued to the tab

with silver epoxy, so the contribution
of that resistance is negligible
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Resistance ratio for Trench MOSFET

VDSS

30V

60V

200V

Rch

30%

10%

5%

Repi

40%

80%

94%

Rsub

30%

10%

1%

The Resistive Components

of the overall RDS(on) Structure
of a Vertical Power MOSFET
RDS(ON) = Rch + Repi + Rsub + RWIRE
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Temperature dependency of On-Resistance, RDS(ON)

RDS(ON) - TC characteristic (2SK3418)

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Important MOSFET Device Design Parameters

MOSFET Package Parasitic

Drain

LD

RTAB

Rgi
N+

P+

Gate LG

RG

Epi
Substrate

NN++

Structure of N-Channel Trench Cell

RWIRE

Ls
Packaging

Source

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Important MOSFET Device Design Parameters

MOSFET Capacitances
Drain

G
Rgi

VDSS

CGD

CDS

Gate

N+

P+

Epi
Substrate

CGS

NN++

Structure of N-Channel Trench Cell

VGSS

Source

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CISS = CGS + CGD

COSS = CDS + CGD
CRSS = CGD

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Important MOSFET Device Design Parameters

MOSFET Body Diode

Drain

ID
Body
Diode
trr

Gate

Rgi

VDSS

N+

P+

Epi
IDR

Substrate

NN++

VGSS

Parasitic NPN
Bipolar Transistor

Structure of N-Channel Trench Cell

Source

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The Characteristics of a MOSFET Body Diode

1.

A parasitic body diode is built in the Power MOSFET between

the source and drain. The maximum current rating of this
diode, IDR, is the same value as the maximum rating of the
MOSFET forward drain current, ID

2.

This diode shows that it has the same characteristic for

forward voltage as an ordinary diode in the case of zero bias for
the gate drive voltage, VGS=0

3.

If the gate drive voltage, VGS, has a positive bias, as in the case
of N-channel MOSFET. Then, VSD will be a voltage that is
determined by the on-resistance RDS(on) (VSD = ID x RDS(on)), as
shown on the figure to the right. Therefore, it is possible to get
very low forward voltage similar to a Schottky barrier diode
(SBD).

4.

By taking advantage of such a characteristic, the body diode

can be used to benefit the application in the following:
a)

23

=0V

Load switches for protection against reverse connection of

battery

b)

Hot swap circuits of redundant method for switching power

supply (n+1)

c)

Replace external diodes in motor driving circuit bridges

d)

Secondary synchronous rectifier circuits in switching power

supplies

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IDR - VSD characteristic (2SK3418)

(N-channel)

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Schottky Barrier Diode

Drain

Body Diode
SBD

Gate
Source

Non-overlap/Dead Time to avoid cross conduction (shoot-through)

Body diode of a synchronous switch conducts during dead time
Body diode is lossy and is slow to turn on/off
A Schottky diode (SBD) is used in parallel with the MOSFET
Reduced the forward voltage drop from ~0.7V to ~0.2V
Reduces losses from body diode turn on and reverse recovery losses
Limits overshoot on turn on

Non-overlap time conduction can be significant at high switching

frequencies

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SBD Reduces Turn-on Spike Noise

Lo:RJK0381DPA
(Built in SBD)
SBD

Lo:RJK0351DPA
(without SBD)
Vgs(L)

Vg(H)
Vds(L)

Suppressing
Spike voltage
VP=27.2V

VP=22.6V

Vds(L)

-17%

Vg(H)

Vgs(L)

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Drain-Source Saturation Voltage, VDS(ON)

VDS(ON) depends on the Gate Drive Voltage, VGS, and the Drain current, ID

VDS(ON) = ID x RDS(ON)

VDS(on) - VGS characteristic

(2SK3418)

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QG, QGD, ig(peak), P(Drive Loss) & Fall Time (tf)

definitions
QG @ (VGS=DVGS)

1. Total gate charge, QG, is the point

where the gate driving voltage, VGS,
becomes equal to the Driver output
voltage (DVGS) at the gate of the
VDS
MOSFET

4.

VGS(on)

VTH

(1)

P(drive loss) = FSW*QG*VGS

3.

QTH

(2)

QGD corresponds to mirror capacitance, CRSS

and its value depends on the power supply
voltage VDS. Recall that CRSS = CGD

QG

Gate Charge
(a)

(RS + rg)*QGD
VGS(on) - VTH

ln VGS(on)
VTH

Input Dynamic Characteristic

(2SK3418)

Q = CISSVGS = integral (IG * dt) = I*t = I*1/FSW

I = Q*FSW
P= IV =Q*FSW *V = C*FSW *V2

QGD is the parameter that greatly influences a

devices switching fall time, tf,
where RS = RDRIVER, RG = RPCB+Rgi:

tf =.

DVGS

VGS (V)

IG(peak) = QG/t

VGS
QGD

VDS (V)

2. QG is the parameter that controls

gate peak current, IG(peak), from the
MOSFET driver and the drive loss,
P(drive loss)

QGS

(3)

5. The fall time, tf, controls the switching loss and tf is computed using formula (3) above. Both QG and QGD are
important items when designing for high frequency operation.
. For high-speed switching (over F SW =100kHz)
applications, the smaller the RON/QG or RON/QGD the more efficiency the MOSFET device will become
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Avalanche Breakdown
It is a phenomenon that can occur in both insulating
and semiconductor materials.
It is a form of electric current multiplication that can
allow very large currents to flow within materials
which are otherwise good insulators.
It is a type of electron avalanche.
The Avalanche process occurs when the carriers in the
transition region are accelerated by the electric field
to energies sufficient to free electron-hole pairs via
collisions with bond electrons.

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Avalanche - Destruction Failure Modes

VIN
IOUT
L

VOUT
IL

When the current through the output inductor is quickly turned

off, the magnetic field of the inductor induces a counter
electromagnetic force, EMF, that can build up a high VDS
voltage across the MOSFET. The full buildup of this induced
voltage may exceed the rated breakdown voltage, VDSS, of
the MOSFET and result in the catastrophic failure of the
MOSFET.
Two failure modes exist when MOSFETs are subjected to
unclamped inductive switching, UIS. These two failure
mechanisms are defined as either 1) the active Mode 1 or 2)
the passive Mode 2.
1.The first, or active Mode 1, results when the avalanche
current actively forces the parasitic bipolar transistor into
conduction and turns it on. Today, MOSFETs are being
manufactured in which the parasitic bipolar transistor never
turns on and Mode 1 failures do not occur
2.The second, or passive Mode 2, results when the
instantaneous chip temperature reaches a critical value. At
this elevated temperature, a meso-plasma forms within the
parasitic NPN bipolar transistor and causes catastrophic
thermal runaway. The passive mechanism is, therefore,
identified as that failure mode not directly attributed to
avalanche currents.

Parasitic Bipolar Transistor

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In either of the first or the second cases, the MOSFET is

destroyed.

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Safe Operation Area, SOA, Definitions

1
2

SOA for the (2SK3418)

30

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Thank You

Renesas Electronics America Inc.

2010 Renesas Electronics America Inc. All rights reserved.