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IC Cost
Cost per die = (cost per wafer) / ((dies per wafer) * yield)
on single chip, or
using many chips interconnected on a printed circuit board
(PCB)
Standard chips
Programmable Logic Devices (PLD)
Custom chips
Standard Chips
Gnd
14
13
12
11
10
7400
Vcc = +5V
00
3
4
5
9
10
12
13
11
7404
7408
x1
x2
x3
7432
PLDs
Custom Chips
Custom chips
Fast, small
Expensive! And takes time to build and manufacture
Initial design
Simulation
Design correct?
Yes
Successful design
Redesign
No
Design specifications
Initial design
Simulation
Redesign
Design correct? No
Pentium bug
Yes
Implement prototype
Yes
Testing
Meets specs?
Yes
Finished product
Make corrections
Minor errors?
No
No
Simulation Phase
Functional simulation
Timing simulation
CAD Tools