Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Chapter 5 Objectives
Wouldnt it be more convenient to have in MARIE
Add 1 (in addition to Add One)?
Why an ISA includes some instructions but not the
others?
Instruction complexity.
Affect the amount of decoding, thus performance.
Opcode
Operand 1
Operand 2
Operand 3
Actual data
Mem. addr. to actual data
Register holding actual data
Reg/mem addr holding addr to
actual data
5
Addressing modes.
Choose any or all: direct, indirect or indexed, etc.
Source: wiki
10
BR2
ALU
Stack
MAR
PC
IR
Control
11
Main
Memory
ALU
Register
File
MAR
PC
IR
Control
12
Main
Memory
Opcode
13
Operand 1
Operand 2
Operand 3
BR1
BR2
ALU
Stack
MAR
PC
IR
Control
16
Main
Memory
17
Z = (X Y) + (W U),
becomes:
Z = X Y W U +
in postfix notation.
18
2 3+ - 6/3
19
2 3+ - 6 3/
20
2 3+ 6 3/ -
21
2 3 + 6 3
found
22
/ -
2 3 + 6 3
23
/ -
2 3 + 6 3
Push operands until another
operator is found.
6
5
24
/ -
2 3 + 6 3
Carry out the operation and
push the result.
25
2
5
/ -
2 3 + 6 3
26
/ -
27
Z = X Y + W U
might look like this:
MULT R1,
MULT R2,
ADD Z,
28
X,
W,
R1,
Y
U
R2
Z = X Y + W U
might look like this:
LOAD R1,
MULT R1,
LOAD R2,
MULT R2,
ADD R1,
STORE Z,
29
X
Y
W
U
R2
R1
Note: One-address
ISAs usually
require one
operand to be a
register.
Z = X Y + W U
looks like this:
LOAD
MULT
STORE
LOAD
MULT
ADD
STORE
30
X
Y
TEMP
W
U
TEMP
Z
Z = X Y W U +
might look like this:
PUSH
PUSH
MULT
PUSH
PUSH
MULT
ADD
PUSH
31
X
Y
W
U
Z
5.4 Addressing
Addressing modes specify where an operand is
located.
The operands in an instructions can be the actual data,
register/memory location holding the data, or
registers/memory location holding address to a mem
location that holds the actual data.
34
35
36
Indirect indexed.
Base/offset.
Self-relative
Auto increment - decrement.
38
39
Chapter 5 Conclusion
ISAs are distinguished according to their bits per
instruction, number of operands per instruction, operand
location and types and sizes of operands.
Instruction format: an opcode with zero or several
operands.
Endianness as another major architectural consideration.
CPU can store data internally based on
1. A stack architecture
2. An accumulator architecture
3. A general purpose register architecture.
40
Chapter 5 Conclusion
Instructions can be fixed length or variable length.
Typically vary in the number of operands.
Size of opcodes can vary too.
41
Immediate
Register
Indirect
Based
Direct
Register Indirect
Indexed
Stack
End of Chapter 5
42
43
44
45
4. Fetch operands.
5. Execute instruction.
6. Store result.
46
47
48
Data dependencies.
Conditional branching.
50