Chapter 9

Bootloader

Learning Objectives

Chapter 9, Slide 2

Need for a bootloader.

What happens during a reset.
Boot modes and processes.
Memory map.

Dr. Naim

What is the bootloader?

VCC

VCC

Boot Config

DMA

L2 Cache

EPROM

EMIF

L1P Cache

Addr
0000
0001
0002
0003
...

CPU
L1D Cache

C6211/C6711

Chapter 9, Slide 3

When the DSP is NOT powered or under

reset the internal program memory is in a
random state.
Dr. Naim

What is the bootloader?

VCC

VCC

Boot Config

DMA

L2 Cache

EPROM

EMIF

L1P Cache

Addr
0000
0001
0002
0003
...

CPU

PC=0003
PC=0000
PC=0001
PC=0002

L1D Cache
C6211/C6711

Chapter 9, Slide 4

When the DSP is powered and the CPU is taken out

of reset the internal memory is still in a random state
and the program will start running for address zero.
Dr. Naim

What is the bootloader?

VCC

VCC

Boot Config

DMA

L2 Cache

EPROM

EMIF

L1P Cache
CPU
L1D Cache
C6211/C6711

Chapter 9, Slide 5

With the boot, a portion of code can be

automatically copied from external to
internal memory.
Dr. Naim

What happens at reset: System timeline

/RS pin

CPU Reset
Device Reset

When the device is held in reset:

The device is initialised to the default state.

Most 3-state outputs are in the high impedance state.

Chapter 9, Slide 6

Dr. Naim

What happens at reset: System timeline

/RS pin

CPU Reset
Device Reset

CPU Reset
Boot load in
operation

On the rising edge of the /RS pin:

The processor checks the boot mode configuration (HD[4:3]) and starts the boot loader.
The EDMA automatically copies 1K bytes from the beginning of CE1 location to the internal program memory starting at address zero.

Chapter 9, Slide 7

Dr. Naim

What happens at reset: System timeline

/RS pin

CPU Reset
Device Reset

CPU Reset
Boot load in
operation

Once the boot loader has finished initialising the internal memory the CPU is taken out of reset.
The CPU starts running from address zero.

Chapter 9, Slide 8

Dr. Naim

C6211 and C6711 Memory map

Chapter 9, Slide 9

The C6211 and C6711 has only one

memory map, MAP0.
Internal memory is always located at
address zero.
Internal memory can be used as either
program or data.

Dr. Naim

C6211 and C6711 Memory map

Chapter 9, Slide 10

Dr. Naim

Boot modes and processes

Two questions need to be answered

about the bootloader, these are:

Chapter 9, Slide 11

What methods of boot are available and

how are they selected?
How does the DSP know what type of
memory it is going to boot from?

Dr. Naim

Bootloader operational modes

The TMS320C6211 and C6711 support

the following boot configurations:
(1)
(2)
(3)
(4)

Host Port Interface (HPI) boot.

8-bit ROM boot.
16-bit ROM boot.
32-bit ROM boot.

Note: with the C6211 and C6711 there is no

no-boot mode as for the other C6000
processors.
Chapter 9, Slide 12

Dr. Naim

Bootloader configuration

The boot mode is selected by pulling the

HD[4:3] pins (HPI data bus pins) high
or low at reset.
Depending on the voltages on this pins
one of the four modes is selected.
HD[4:3]
00
01
10
11

Chapter 9, Slide 13

Boot mode
HPI boot
8-bit ROM boot
16-bit ROM boot
32-bit ROM boot

Dr. Naim

Endianess configuration

The endian mode is determined at the

same time as boot mode.
Pulling pin HD[8] high or low selects the
following endian modes.
HD[8]
0
1

Device operation
Big endian
Little endian

Note: ensure that the software development

tools are also configured with the same
endian type as the hardware.
Chapter 9, Slide 14

Dr. Naim

Clock mode configuration

The input clock mode is also determined at

the same time as boot mode.
Pulling CLKMODE0 pin high or low
selects the following modes.
CLKMODE0
0
1

Chapter 9, Slide 15

PLL frequency multiplier

No multiplication
Input frequency is multiplied by 4

Dr. Naim

Boot process: HPI boot mode

In this mode the following sequence is

used:

The CPU is held in reset while the remaining

of the device is released.
The host processor initialises the CPUs
memory space through the HPI.
When all the necessary memory is initialised
the host processor takes the CPU out of reset
by writing a 1 to the DSPINT bit filed of
the Host Port Interface Control (HPIC)
register.
17
DSPINT

Chapter 9, Slide 16

HPIC
Dr. Naim

Boot process: HPI boot mode

/RS

Boot Config

DMA

L2 Cache

DRAM

EMIF

HOST

HPI

L1P Cache
CPU
L1D Cache

C6211/C6711

Chapter 9, Slide 17

Dr. Naim

Boot process: HPI boot mode

Chapter 9, Slide 18

Question: How does the host processor

check that the memory has been
initialised correctly?
Answer: The host can read and write to
any address so it can check by reading the
initialised memory.

Dr. Naim

Boot process: HPI boot mode

Chapter 9, Slide 19

Question: If an external memory needs to

be initialised via the HPI how do you
ensure that the EMIF is set correctly?
Answer: The first thing the Host should
do is to write the EMIF register then
write to the external memory locations.

Dr. Naim

Boot process: ROM boot mode

In this mode the following sequence is

used:

Chapter 9, Slide 20

The CPU is held in reset while the

bootloader operates.
The bootloader copies 1Kbytes from CE1
with the default settings to internal memory
at address zero.
CPU is taken out of reset.
CPU starts running code from address zero.

Dr. Naim

Boot process: ROM boot mode

VCC

/RS

Boot Config

EMIF

ROM
DMA

DRAM

L2 Cache

L1P Cache
CPU
L1D Cache
C6211/C6711

Chapter 9, Slide 21

Dr. Naim

Chapter 9
Bootloader
- End -