CHAPTER 6

DESIGNING COMBINATIONAL LOGIC

CIRCUITS

Prepared by Azhani binti

Hashim

STATIC CMOS DESIGN

Difference between combinational
logic circuit and sequential logic
circuit.

STATIC CMOS DESIGN

Difference between combinational
logic (nongenerative) circuit and
sequential logic (regenerative)
circuit.
Output for combinational logic circuit
depends on current input signal by some
Boolean expression. No intentional
connection between output and input.

STATIC CMOS DESIGN

Difference between combinational logic
(nongenerative) circuit and sequential logic
(regenerative) circuit.
the output for regenerative circuit is not only a
function of the current input data, but also of
previous values of the input signals. This is
accomplished by connecting one or more outputs
intentionally back to some inputs. The circuits
remembers past events and has a sense of history.
Example: ?

STATIC CMOS DESIGN

The most widely used logic style is static
CMOS.
The primary advantage of the CMOS structure
is robustness (i.e, low sensitivity to noise),
good performance, and low power
consumption with no static power dissipation.
The complementary CMOS circuit style are
called static circuits due to each gate output
is connected to either V DD or VSS (via a lowresistance path) at every point of time.

COMPLEMENTARY CMOS
A static CMOS gate is a combination
of two networks, called the pull-up
network (PUN) and the pull-down
network (PDN).

COMPLEMENTARY CMOS
a generic N input logic gate where all
inputs are distributed to both the
pull-up and pull-down networks.

COMPLEMENTARY CMOS
The function of the PUN is
to provide a connection
between the output and VDD
anytime the output of the
logic gate is meant to be 1.
The output of the logic gate
is 1.
The function of the PDN is
to connect the output to
VSS when the output of the
logic gate is meant to be 0.
The output of the logic gate
is 0.

COMPLEMENTARY CMOS
A transistor can be thought of as a
switch controlled by its gate signal.
An NMOS switch is on when the
controlling signal is high and is off
when the controlling signal is low.
A PMOS transistor acts as an inverse
switch that is on when the controlling
signal is low and off when the
controlling signal is high.

COMPLEMENTARY CMOS
The PDN is constructed using NMOS
devices, while PMOS transistors are
used in the PUN.
The primary reason for this choice is
that NMOS transistors produce
strong zeros, and PMOS devices
generate strong ones.

COMPLEMENTARY CMOS

An NMOS device pulls the output all the

way down to GND, while a PMOS lowers
the output no further than |VTp|. The
PMOS turns off at that point, and stops
contributing discharge current.

COMPLEMENTARY CMOS

A PMOS switch succeeds in charging the

output all the way to VDD, while the
NMOS device fails to raise the output
above VDD-VTn.

COMPLEMENTARY CMOS

NMOS devices connected in series

corresponds to an AND function.
NMOS transistors connected in
parallel represent an OR function.
How about PMOS?

COMPLEMENTARY CMOS
The pull-up and pull-down networks
of a complementary CMOS structure
are dual networks.
The number of transistor
required to implement
N-input is 2N.

CMOS CIRCUIT FROM BOOLEAN

FUNCTION

+ : parallel
: series

http://www.ittc.ku.edu/~jstiles/312/handouts/section_10_3_CMOS_Logic_Gate_Circuits_package.pdf

CMOS CIRCUIT FROM BOOLEAN

FUNCTION

CMOS CIRCUIT FROM BOOLEAN

FUNCTION

+ : parallel
: series

http://www.ittc.ku.edu/~jstiles/312/handouts/section_10_3_CMOS_Logic_Gate_Circuits_package.pdf

CMOS CIRCUIT FROM BOOLEAN

FUNCTION

CMOS CIRCUIT FROM BOOLEAN

FUNCTION

http://www.ittc.ku.edu/~jstiles/312/handouts/section_10_3_CMOS_Logic_Gate_Circuits_package.pdf

CMOS CIRCUIT FROM

BOOLEAN FUNCTION
PMOS

+ : parallel
: series

CMOS CIRCUIT FROM BOOLEAN

FUNCTION

NMOS

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ara es
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+ : ser

http://www.ittc.ku.edu/~jstiles/312/handouts/section_10_3_CMOS_Logic_Gate_Circuits_package.pdf

CMOS CIRCUIT FROM

BOOLEAN FUNCTION

EXERCISE
1. Draw the schematic of CMOS static
logic circuit for the following
equation.
i.
ii.
iii.

?
Schematic logic circuit diagram

Layout

STICK DIAGRAM
Stick diagram is a simple diagram and is a means
of capturing topography and layer information.
Stick diagrams convey layer information through
colour codes or monochrome encoding.

Stick diagram
Schematic logic
circuit diagram

Layout

STICK DIAGRAM
Schematic logic
circuit diagram

Stick diagram

STICK DIAGRAM

STICK DIAGRAM (EULER PATH)

Step 1 : Identify source and drain for each transistor.
Step 2 : Draw Euler path for PUN and PDN.
(both path must go through transistors in same order.)
Step 3 : Follow the Euler path to draw stick diagram.

STICK DIAGRAM
Schematic logic
circuit diagram

Layout
Stick diagram

STICK DIAGRAM (EULER PATH)

Step 1 : Identify source and drain for each transistor.
Step 2 : Draw Euler path for PUN and PDN.
(both path must go through transistors in same order.)
Step 3 : Follow the Euler path to draw stick diagram.

STICK DIAGRAM
Schematic logic
circuit diagram
Stick diagram

Layout

STICK DIAGRAM (EULER PATH)

Step 1 : Identify source and drain for each transistor.
Step 2 : Draw Euler path for PUN and PDN.
(both path must go through transistors in same order.)
Step 3 : Follow the Euler path to draw stick diagram.

STICK DIAGRAM
Schematic logic
circuit diagram
Stick diagram

Layout

EXERCISE
1. Draw the stick diagram for the
following equation using CMOS
circuit.
i.
ii.
iii.
iv. Y = A + B

CMOS INVERTER GATE

Draw CMOS Inverter Gate.

CMOS NAND GATE

Draw CMOS Nand Gate

CMOS AND GATE

Draw CMOS And Gate

PASS-TRANSISTOR LOGIC
Pass-transistor logic is alternative to
complementary CMOS.

Primary input drive gate terminal as well as

source/drain terminal.
Require only ____ transistor.
Reduced number of devices give lower in
capacitance.

PASS-TRANSISTOR LOGIC
However, NMOS transistor only effective at
passing logic ___ but poor when passing
logic ___.

PASS-TRANSISTOR LOGIC

VTC OF PASS TRANSISTOR AND

GATE

B=VDD,top pass transistor is ON.

Bottom transistor is OFF. Output will
follow input A up to VDDVTn.

VTC OF PASS TRANSISTOR AND

GATE

A=VDD and B makes transition from 0 - 1. Top pass

transistor will be OFF and bottom pass transistor will
be ON until output from inverter is close to logic 0.
Once B entering logic 1, output inverter will be logic
0, bottom pass transistor will turned off and top
transistor will be ON.

DIFFERENTIAL PASS
TRANSISTOR LOGIC
A differential pass-transistor logic
called CPL or DPL is used for high
performance design.

DIFFERENTIAL PASS
TRANSISTOR LOGIC
Properties / benefit of CPL gates:
Designing complex gate such as XOR or adder
using differential style are efficiently with a small
number of transistor.
CPL belongs to class of static gates because the
output-defining nodes are always connected to VDD
or GND through a low resistance path.
The design is very modular and in the same
topology. This makes the design of a library of
gates very simple and more complex gates can be
built by cascading the standard pass-transistor
modules.

ROBUST AND EFFICIENT PASSTRANSISTOR DESIGN

Pass-transistor logic suffers from
static power dissipation and reduced
noise margin. This is due to high
input only charges up to VDDVTn.
Solutions:
1. Level restoration
2. Multiple-threshold transistor
3. Transmission-gate logic

ROBUST AND EFFICIENT PASSTRANSISTOR DESIGN

1. Level restoration
Solution to voltage drop (VDDVTn) is the
use of a level restorer which is a PMOS
configured in a feedback path.

ROBUST AND EFFICIENT PASSTRANSISTOR DESIGN

1. Level restoration
B=VDD and A=0V
resulting X at 0V, OUT
is VDD and Mr OFF.
A makes to VDD, Mn
only charges up X to
VDDVTn. Enough to
switch inverter to
logic 0, Mr will be ON,
X then will pull to VDD.
Eliminates any static
power dissipation.

ROBUST AND EFFICIENT PASSTRANSISTOR DESIGN

1. Level restoration
But when X transition from VDD
to 0, level restorer will pull X to
VDD.
Therefore, the pull-down device
(Mn) must be stronger than the
pull-up device (Mr).
Solution: voltage at X must be
pulled down below VM, to switch
the inverter and shut off Mr.
This is done be increasing
resistance at Mr so that node X
able to pulled down below VM.
Resistance of Mr depends on
transistor sizing.

ROBUST AND EFFICIENT PASSTRANSISTOR DESIGN

2. Multiple-Threshold Transistor
Using zero threshold devices for the NMOS
pass-transistor eliminates most of the
threshold drop and passes a signal close to VDD.
All other devices other that the pass transistors
are using standard high-threshold devices.

ROBUST AND EFFICIENT PASSTRANSISTOR DESIGN

2. Multiple-Threshold Transistor
However, there are subthreshold currents
(potential sneak dc-current path) can flow
through the pass-transistor.
These leakage path is not critical when the
device in switching constantly, but pose a
significant energy-overhead when the circuit is
in idle state.
2.5 V

ROBUST AND EFFICIENT PASSTRANSISTOR DESIGN

3. Transmission Gate Logic
The mose widely-used solution.
The approach is to use an NMOS to pull-down
AND a PMOS to pull-up.
When C = 1, both MOSFETs are ON, allowing
the signal to pass through the gate. When C =
0, open circuit between nodes A and B.

ROBUST AND EFFICIENT PASSTRANSISTOR DESIGN

3. Transmission Gate Logic
Transmission gates can be used to build some
complex gates very efficiently.

ROBUST AND EFFICIENT PASSTRANSISTOR DESIGN

3. Transmission Gate Logic
This transmission gate XOR requires only six
transistor (including inverter for B*) compare to
twelve transistor when using complementary
implementation.
When B = 1, only inverter operational while
transmission gate is off.
When B = 0, only transmission
gate is operational while
inverter is off.

DYNAMIC CMOS DESIGN

Dynamic logic circuit is an approach to
avoid static power consumption by using:
1. PDN network
2. clock input.
3. a sequence of precharge and
evaluation phases.
. The operation of circuit is divided into
two major phases : precharge and
evaluation, determined by a clock signal.

DYNAMIC CMOS DESIGN

DYNAMIC CMOS DESIGN

Precharge
When CLK = 0, OUT is precharged to
VDD. (MP is on and Me is off). Pull-down
path is disable. No static power during
precharge period.

Evaluation
When CLK = 1, MP is off and Me is on.
If the inputs are such that the PDN is
conduct, OUT will get GND.
If the inputs are such that the PDN is
off, OUT will have the precharged value
remains stored on the CL(junction
capacitances, wiring capacitance and
input capacitance).

DYNAMIC CMOS DESIGN

During precharge phase
(CLK=0), OUT is precharged to
VDD regardless of the input
values since evaluation device
is turned off.
During evaluation (CLK=1), a
conducting path is created
between OUT and GND if and
only if AB+C is TRUE.
Otherwise, the output remains
at VDD.

DYNAMIC CMOS DESIGN

Important properties:
Logic function implemented by PDN (NMOS) just as for
static CMOS.
Number of transistor is substantially lower than static
circuit. N+2 vs 2N.
It is non-rationed. The sizing of PMOS not important.
It only consumes dynamic power. Ideally, no static
power consumption. But the overall power dissipation
can be significantly higher than static circuit.
Faster switching speeds due to lower number
transistors per gate. Second reason is no short circuit
current. All the current provided by the PDN towards
discharging CL.

DYNAMIC CMOS DESIGN

Main advantages of dynamic logic are:
Increased speed.
Reduced implementation area.

After precharge phase, the OUT is high

resulting, tpLH =0. (low to high transition)
During evaluation phase, PDN network
need to discharging of the CL. (high to low
transition). tpHL is proportional to CL and
current-sinking capabilities of PDN network.

DYNAMIC CMOS DESIGN

DYNAMIC CMOS DESIGN

For power dissipation, dynamic logic
has significant advantage due to
three reason:
1. The physical capacitance is lower due
to fewer transistors used.
2. Dynamic logic have one transition per
clock cycle.
3. No short circuit power since no pull-up
path when the gate is evaluating.

ISSUES IN DYNAMIC CMOS

DESIGN
Dynamic logic clearly can result in high
performance solutions compare to static
circuits.
However, there are several consideration
must be taken into account for it to
function properly:
Charge leakage
Charge sharing
Backgate/capacitive coupling
Clock feedthrough

ISSUES IN DYNAMIC CMOS

DESIGN
Charge leakage
During evaluation
phase, if the PDN
network is off, output
should ideally remain
at the precharged
state of VDD. However,
this charge gradually
leaks away due to
leakage currents.

ISSUES IN DYNAMIC CMOS

DESIGN

Charge leakage

(1) : reverse-biased diode of M1.

(2) : sub-threshold leakage of M1.
Therefore, dynamic logic require
minimal clock rate at kHz. This makes
usage of dynamics techniques not
suitable for low perfomance product.
(3) : reverse-biased diode of Mp .
(4) : sub-threshold leakage of Mp .
However, this leakage current for
PMOS counteracts the leakage of the
PDN. As a result, output is going to be
set by the resistive divider from pulldown and pull-up.

ISSUES IN DYNAMIC CMOS

DESIGN

ISSUES IN DYNAMIC CMOS

DESIGN
Charge sharing
During precharge phase;
OUT is precharged to VDD.
Assume all input are 0,
capacitance Ca and Cb is
discharged.

During evaluation phase;

B remain 0 will A going to 1.
OUT need to remains VDD, but
the charge stored on CL
redistributed over CL and Ca.

ISSUES IN DYNAMIC CMOS DESIGN

Capacitive Coupling
Consider a circuit of a dynamic
two-input NAND gate drives a
static NAND gate.
When In transition from low to
high, Out2 will go low.
However, this transition
couples capacitively to Out1,
through gate-source and gate
drain capacitances of M4. This
resulting Out1 will discharged
and voltage drop significantly.
If the voltage drop is large
enough, Out2 may not to go low
giving incorrect result.
When designing and laying out
dynamic circuits, special care is
needed to minimize capacitive
coupling.

ISSUES IN DYNAMIC CMOS

DESIGN
Clock-Feedthrough
Special case of capacitive coupling.
An effect caused by the capacitive coupling
between the clock input of the precharge
device and the dynamic output node. The
coupling capacitance consist of:
1. Gate-to-drain capacitance
2. Overlap capacitance
3. Channel capacitance

This capacitive coupling causes the Out 1 to rise

above VDD on low-to-high transition.