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Behavioral Modeling

Modeling Behavior
Architecture body
describes an implementation of an entity
may be several per entity
Behavioral architecture
describes the algorithm performed by the module

architecture rtl of ex is
concurrent declaration part
begin
concurrent VHDL
process (...)
sequential declaration part
begin
sequential VHDL
end process;
concurrent VHDL
end;

Concurrent VHDL
constructions

Process statement
When else statement
With select statement
Signal declaration
Block statement

Assignments are executed sequentially


inside processes.

Sequential VHDL
constructions

If-then-else statement
Case statement
Variable statement
Variable assignment
Loop statement
Return statement
Null statement
Wait statement

Process Statement

The process statement is a concurrent statement that defines a specific


behavior to be executed when the process becomes active.
The behavior of the process is described with a set of sequential
statements.
It is characterized by the presence of IF, WAIT, CASE, or LOOP, and
by a sensitivity list (except when WAIT is used).
VARIABLES are optional.
General Form is :
[label:] PROCESS (sensitivity list)
[VARIABLE name type [range] [:= initial_value;]]
BEGIN
(sequential code)
END PROCESS [label];

A simple Example
entity Xor_gate is
port (in1, in2 : in bit; Out1 : out bit);
end Xor_gate ;
architecture behavioral of Xor_gate is
begin
process (In1, in2)
begin
Out1 <= In1 xor In2;
end process;
end behavioral;

architecture Behavioral_Desc of Adder is


begin
process (A, B)
begin
Sum <= A xor B ;
Cout <= A and B;
end process;
end Behavioral_Desc;

Process Statement
If there are several processes in an architecture, they are
executed concurrently.
A process is either active or suspended.
A process becomes active when any of the signal read by the
process changes its value.
All active processes are executed concurrently
A process may be suspended upon execution of a wait
statement in the process. The process remains suspended until
its reactivation condition is met.

half subtractor
entity h_subtractor is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
difference : out STD_LOGIC;
borrow : out STD_LOGIC );
end h_subtractor;
architecture rtl of h_subtractor is
begin
process(a,b)
begin
difference <= a xor b;
borrow <= (not a) and b;
end process;
end rtl;

Conditional Control
These sequential statements provide conditional control i.e
statements are executed when a given condition is true
VHDL provides two types of conditional control statements
if then elsif
case end case

If Statement
General form is
if condition then
statement
elsif condition then
statement
else
statement
end if;

Case Statement
General Form is
case expression is
when value =>
statements
when value | value =>
statements
when discrete_range =>
statements
when others =>
statements
end case;

MUX 4*1
entity mux_case is
port( a,b,c,d : in STD_LOGIC;
sel :in STD_LOGIC_vector (0 to 1);
z : out STD_LOGIC );
end mux_case;
architecture rtl of mux_case is
begin
Process (sel,a,b,c,d)
begin
case sel is
when "00" => z <= a;
when "01" => z <= b;
when "10" => z <= c;
when others =>z <= d;
end case;
end process;
end rtl;

entity mux4_1 is
port( a,b,c,d : in STD_LOGIC;
sel : in STD_LOGIC_vector(0 to 1);
z : out STD_LOGIC );
end mux4_1;
architecture rtl of mux4_1 is
begin
process (sel)
begin
if sel= '0' & '0' then
z<= a;
elsif sel= "01" then
z<= b;
elsif sel= "10" then
z<= c;
else
z<= d;
end if;
end process;
end rtl;

entity jk_ff is
port(

j, k, clk : in STD_LOGIC;
q : inout STD_LOGIC );

end jk_ff;
architecture rtl of jk_ff is
begin
process (j, k, clk)
begin
if clk = '1' then
if j ='0' and k = '0' then
q <= q;
elsif j ='0' and k = '1' then
q <= '0';
elsif j ='1' and k = '0' then
q <='1';
elsif j ='1' and k = '1' then
q <= not q;
end if;
end if;
end process;
end rtl;

entity jk_ff is
port(

j, k, clk : in STD_LOGIC;
q : inout STD_LOGIC );

end jk_ff;
architecture rtl of jk_ff is
signal input: std_logic_vector(1 downto 0);
begin
process (clk)
begin
if clk = '1' then
case input is
when "00" => q <= q;
when "01" => q <= '0';
when "10" => q <= '1';
when "11" => q <= not q;
when others => null;
end case;
end if;
input <= J & K;
end process;
end rtl;

Architecture Declaration

entity fulladder_bh is
port ( A, B, Cin : in bit;
Sum, Cout : out bit);
end fulladder_bh;
architecture behavioral of fulladder_bh is
begin
process (A , B, Cin)
begin
if ( A = 0 and B = 0 and Cin = 0) then
Sum <= 0;
Cout <= 0;
elsif ( A = 0 and B = 0 and Cin = 1) then
Sum <= 1;
Cout <= 0;
elsif ( A = 0 and B = 1 and Cin = 0) then
Sum <= 1;
Cout <= 0;
elsif ( A = 0 and B = 1 and Cin = 1) then
Sum <= 0;
Cout <= 1;
elsif ( A = 1 and B = 0 and Cin = 0) then
Sum <= 1;
Cout <= 0;

elsif ( A = 1 and B = 0 and Cin = 1) then


Sum <= 0;
Cout <= 1;
elsif ( A = 1 and B = 1 and Cin = 0) then
Sum <= 0;
Cout <= 1;
else
Sum <= 1;
Cout <= 1;
end if;
end process;
end behavioral;

19/26

Example
The following process implements a simple OR gate---- this process is sensitive to signals In1 and In2
Or_process : process (In1, In2)
begin
Output <= In1 or In2;
end process;
--- this is equivalent to
Or_process : process
begin
Output <= In1 or In2;
wait on In1, In2;
end process;

Wait Statement
Three kind of reactivation condition can be specified in a wait
statement
timeout
wait for time-expression;
condition
wait until Booleanexpression;
signal sensitivity
wait on signal-list;
Conditions can be mixed.
- wait on A, B until Enable = 1;
If a process is always sensitive to one set of signals, it is
possible to designate sensitivity signals using a sensitivity list.
It is illegal to use wait statement in a process with a sensitivity
list.
Every process is executed once upon initialization.

Some examples of wait statements are


wait on A, B, C; -- statement 1
wait until (A = B); -- statement 2
wait for 10ns; -- statement 3
wait on CLOCK for 20ns; -- statement 4
wait until (SUM > 100) for 50 ms; -- statement 5

Details of the waits types


Wait until a=1; means that, for the wait condition to be satisfied and execution
of the code to continue, it is necessary for signal a to have an event, i.e. change
value, and the new value to be 1, i.e. a rising edge for signal a.
Wait on a,b; is satisfied when either signal a or b has an event (changes value).
Wait for 10 ns; means that the simulator will wait for 10 ns before continuing
execution of the process.
The starting time point of the waiting is important and not the actual changes
of any signal value.
It is also permissible to use the wait for command as follows:
constant period:time:=10 ns;
wait for 2*period;
The wait alternatives can be combined into: wait on a until b=1 for 10 ns;, but
the process sensitivity list must never be combined with the wait alternatives
Example: wait until a=1 for 10 ns;
The wait condition is satisfied when a changes value or after a wait of 10 ns
(regarded as an or condition).

Examples of wait statement


type a: in bit; c1, c2, c3: out bit;

Example 1
process (a)
begin
c1<= not a;
end process;

Example 2
process
begin
c2<= not a;
wait on a;
end process;

Example 3
process
begin
wait on a;
c3<= not a;
end process;

10
C1
C2
C3

20

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50

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time [ns]