Chapter Three

Introduction to VLSI design

and
VLSI design process

Outline
VLSI Design Process
Design domains
Layout layers and design rules
CMOS scaling

VLSI Design Process

VLSI design process is an iterative process that refines

an idea to a manufacturable device through at least five
levels of design abstraction.
A system behavior should be understood from its top
level (chip as a whole) to the simple transistor level in the
VLSI design process. Systems behavior is the high level
abstraction while transistors functionality is the lowest
level of abstraction.
Basically, there are five levels of abstraction:
Functional or architectural,
Register transfer level (module or functional
block),
Logical design,
Circuit design,
Physical design.
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VLSI Design Domains

MODELING
A digital system can be considered as any digital
circuit that processes or stores information.
A model represents information of a system which is
relevant and abstracts away from irrelevant details.
There may be several models of the same system,
since different information is relevant in different
contexts.
Models may
concentrate on representing the function of
the system,
represent the way in which the system is
composed of subsystems,
deal on how the system is laid out in
physical space.
4

Contd
Models are made to achieve maximum reliability in the
design process for minimum cost and design time.
We need to ensure that requirements are clearly
specified and understood, that subsystems are used
correctly and that designs meet the requirements.
A major contributor to excessive cost and delays is
having to revise a design after manufacture to correct
errors.
In VLSI design process, there are three distinct design
domains:
Behavioral domain: specifies the software
implementation of the systems functionality.
Structural domain: specifies how modules of
the system are connected together to affect
the prescribed behavior.
Physical domain: specifies the layout
used to
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Domains and Levels of Modeling

Functional

Structural

high level of
abstraction
low level of
abstraction

Geometric
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Gajskis Y-chart
Behavior

Structural
Processors, memories

Sequential programs

Registers, MUXs

Register transfers

Gates, flip-flops

Each axis represents type of

description

Transistors

Logic equations/FSM
Transfer functions

Behavioral

Defines outputs as function of

inputs (Algorithms)

Structural

Implements behavior by
connecting components with
known behavior

Cell Layout
Modules
Chips
Boards

Physical

Gives size/locations of
components and wires on
chip/board

Physical

Layout Layers and Design Rules

IC layout (or IC mask layout or mask design) is
the representation of an IC in terms of planar
geometric shapes which correspond to the
patterns of metal, oxide, or semiconductor layers
that make up the components of the IC.
A layout engineers job is to place and connect all
the components that make up a chip so that they
meet all the set criteria. Typical goals are
performance, size, and manufacturability.
The layout must pass a series of checks in a
process known as verification.

The two most common checks are design rule checking

(DRC), and layout versus schematic (LVS).

When all verification is complete the data is

translated into an industry standard format and
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sent to a semiconductor foundry

Contd
Layout layers of an
inverter cell with external
connections
Inverter Cell
Vdd

Metal2

Contact

Metal1

Via

polysilicon
p/n diffusion
GND

External
Connections
9

Contd

Design rules are a series of parameters provided

by semiconductor manufacturers that enable the
designer to verify the correctness of his/her
mask set.
Design rules are specific to a particular semiconductor
manufacturing process. Design rules are the effective
interface between the circuit/system engineer and
fabrication engineer.
Design rules allow the translation of circuit design
concepts in symbolic form into actual geometry in
silicon.
The main objective of DRC is to achieve a high overall
yield and reliability for the design.
Some examples of DRCs in VLSI design include:
Well to well spacing,
Minimum channel length,
10

Contd
Categories of design rules
Size rules, such as minimum width: The dimensions of
any component (shape), e.g., length of a boundary
edge or area of the shape, cannot be smaller than given
minimum values. These values vary across different
metal layers.
Separation rules, such as minimum separation: Two
shapes, either on the same layer or on adjacent layers,
must be a minimum (rectilinear or Euclidean diagonal)
distance apart.
Overlap rules, such as minimum overlap: Two
connected shapes on adjacent layers must have a
certain amount of overlap due to inaccuracy
of mask
11

Contd

Categories of design rules

: smallest meaningful technologydependent unit of length

a
c

Minimum Width: a
Minimum Separation: b, c, d
e

Minimum Overlap: e
d

12

Contd
Types of constraints
Technology constraints enable fabrication for a specific
technology node and are derived from technology
restrictions. Examples include minimum layout widths
and spacing values between layout shapes.
Electrical constraints ensure the desired electrical
behavior of the design. Examples include meeting
maximum timing constraints for signal delay and
staying below maximum coupling capacitances.
Geometry (design methodology) constraints are
introduced to reduce the overall complexity of the
design process. Examples include the use of preferred
wiring directions during routing, and the placement of
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standard cells in rows.

CMOS Scaling
The only constant in VLSI is constant
change
Feature size shrinks by 30% every 2-3
years
Transistors become cheaper
Transistors become faster
Wires do not improve
(and may
get worse)
S 2
10

Scale factor S

Typically
Technology nodes

Feature Size ( m)

10

6
3
1.5

0.8

0.6
0.35

0.1

1965

1970

1975

1980

1985

Year
14

1990

1995

0.25
0.18
0.13
0.09

2000

2005

Device Scaling
Parameter
L: Length

Sensitivity

Dennard Scaling
1/S

W: Width

1/S

tox: gate oxide thickness

1/S

VDD: supply voltage

1/S

Vt: threshold voltage

1/S

NA: substrate doping

Ion: ON current
R: effective resistance
C: gate capacitance
: gate delay
f: clock frequency
E: switching energy / gate
P: switching power / gate
A: area per gate
Switching power density
Switching current density

W/(Ltox)
(VDD-Vt)2
VDD/Ion
WL/tox
RC
1/
CVDD2
Ef
WL
P/A
Ion/A

S
1/S
1
1/S
1/S
S
1/S3
1/S2
1/S2
1
S
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Interconnect Scaling
Parameter

Sensitivity

Scale Factor

w: width

1/S

s: spacing

1/S

t: thickness

1/S

h: height

1/S

Dc: die size

Dc

Rw: wire resistance/unit length

1/wt

S2

Cwf: fringing capacitance / unit length

t/s

Cwp: parallel plate capacitance / unit length

w/h

Cw: total wire capacitance / unit length

Cwf + Cwp

twu: unrepeated RC delay / unit length

RwCw

S2

twr: repeated RC delay / unit length

sqrt(RCRwCw)

sqrt(S)

Crosstalk noise

w/h

Ew: energy per bit / unit length

CwVDD2

1/S2

16

Contd

Scaling Implications
Improved Performance
Improved Cost
Interconnect Woes
Power Woes
Physical Limits
The basic idea of scaling is to reduce the
dimensions of the MOS transistors and wires
(interconnects) connecting them in the
integrated circuit.
The three most common scaling models are:
Constant field scaling: all the parameters in the
MOSFET are scaled by the factor except supply
voltage VDD and gate oxide thickness tox.

Constant voltage scaling: the supply voltage V DD and

gate oxide thickness tox are scaled down by .
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Combined voltage and dimension scaling.

Difficulties arising due to MOSFET

Scaling
Higher sub-threshold
conduction
Increased gate-oxide leakage
Increased junction leakage
Lower output resistance
Interconnect capacitance
Heat production
Process variations
18

Contd
International Technology Roadmap for
Semiconductors (Semiconductor Industry
Association) forecast

19

Summary of VLSI Design

System Specification
Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;

Functional Design
and Logic Design

Circuit Design

Physical Design

Chip Planning

Placement

Clock Tree Synthesis

Physical Verification
DRC
LVS

Signal Routing
Fabrication
Timing Closure
Packaging and Testing

Chip

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