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COMPLETE
INSTRUCTION
Overview
Some Fundamental
Concepts
Fundamental Concepts
Processor Organization
Internalprocessor
bus
Controlsignals
PC
Instruction
Address
lines
MDR HAS
TWO INPUTS
AND TWO
OUTPUTS
decoderand
MAR
controllogic
Memory
bus
MDR
Data
lines
IR
Datapath
Y
R0
Constant4
Select
MUX
Add
ALU
control
lines
Sub
R n 1
ALU
Carryin
XOR
TEMP
Z
Fundamental Concepts
MDR-2 I/P & 2 O/P
MAR- I/P from internal bus and o/p is
connected to external bus
Data bus & address bus line are connected to
internal processor bus via MDR &MAR
Control line of memory bus are connected to
instruction decoder and control logic block and
it is responsible for issuing signal that control
all the units
Fundamental Concepts
Three
Fundamental Concepts
Data are transferred from one register to
another register via ALU
Instruction decoder and control logic unit is
responsible for implementing action specified
by instruction loaded in IR
Decoder generate ctrl signal to select register
involved & direct the transfer of data
Register,ALU & interconnectcng bus are
collectively referred as Datapath
Fundamental Concepts
Instruction
a)
b)
c)
d)
execution Operation:-
Register Transfers
Register Transfers
Internalprocessor
bus
Riin
Ri
Riout
Yin
Y
Constant4
Select
MUX
A
B
ALU
Zin
Z
Zout
Figure7.2.InputandoutputgatingfortheregistersinFigure7.1.
Register Transfers
I/p
When
Register Transfers
Transfer
Register Transfers
or
Figure
Register Transfers
All operations and data transfers are controlled by the processor clock.
Bus
0
D
1
Q
Ri in
Riout
Clock
Figure7.3.
Figure 7.3.Inputandoutputgatingforoneregisterbit.
Input and output gating for one register bit.
Performing an Arithmetic or
Logic Operation
Performing an Arithmetic or
Logic Operation
R1out, Yin
R2out, SelectY, Add, Zin
Zout, R3in
MDRoutE
MDRout
Internalprocessor
bus
MDR
MDRinE
MDRin
Figure7.4.
Figure 7.4. ConnectionandcontrolsignalsforregisterMDR.
Connection and control signals for register MDR.
MDR in
Processor
MAR [R1]
Start a Read
operation on the
memory bus
Wait for the MFC
response from the
memory
Load MDR from the
memory bus
R2 [MDR]
MDR out, R2 in
STORING A WAORD IN
MEMORY
MOVE R2,(R1)
R1 out , MAR in
Desired address(R1)
is loaded into MAR
Data to be written are
loaded into MDR &
Write command is
issued
Execution of a Complete
Instruction
Add
(R3), R1
Fetch the instruction
Fetch the first operand (the contents of the
memory location pointed to by R3)
Perform the addition
Load the result into R1
Architecture
Internalprocessor
bus
Riin
Ri
Riout
Yin
Y
Constant4
Select
MUX
A
B
ALU
Zin
Z
Zout
Figure7.2.InputandoutputgatingfortheregistersinFigure7.1.
Execution of a Complete
Instruction
Internalprocessor
bus
Add (R3), R1
Controlsignals
PC
Step A ction
1
MDRout , IR in
R1out , Y in , WMF C
Instruction
Address
lines
decoderand
MAR
controllogic
Memory
bus
MDR
Data
lines
IR
Y
R0
Constant4
Select
MUX
Add
ALU
control
lines
Sub
R n 1
ALU
Carryin
XOR
TEMP
Figure7.1.Singlebusorganizationofthedatapathinsideaprocessor.
Execution of Branch
Instructions
A
Execution of Branch
Instructions
StepAction
1
MDR out , IR in
Offset-field-of-IR
out, Add, Zin
Multiple-Bus Organization
BusA
BusB
BusC
Incrementer
PC
Register
file
MUX
Constant4
A
ALU R
B
Instruction
decoder
IR
MDR
MAR
Memorybus
datalines
Address
lines
Multiple-Bus Organization
StepAction
1
WMFC
MDRoutB, R=B,IR in
Figure 7.9.
Control sequence for the instruction. Add R4,R5,R
for the three-bus organization in Figure 7.8.
Quiz
Internalprocessor
bus
Controlsignals
What
is the control
sequence for
execution of the
instruction
Add R1, R2
including the
instruction fetch
phase? (Assume
single bus
architecture)
PC
Instruction
Address
lines
decoderand
MAR
controllogic
Memory
bus
MDR
Data
lines
IR
Y
R0
Constant4
Select
MUX
Add
ALU
control
lines
Sub
R n 1
ALU
Carryin
XOR
TEMP
Z
Figure7.1.Singlebusorganizationofthedatapathinsideaprocessor.
Hardwired Control
Overview
To
CLK
Controlstep
counter
External
inputs
IR
Decoder/
encoder
Condition
codes
Controlsignals
Figure7.10.Controlunitorganization.
CLK
Controlstep
counter
Reset
Stepdecoder
T 1 T2
Tn
INS1
External
inputs
INS2
IR
Instruction
decoder
Encoder
Condition
codes
INSm
Run
End
Controlsignals
Figure7.11. Separationofthedecodingandencodingfunctions.
Generating Zin
Zin = T1 + T6 ADD + T4 BR +
Branch
T4
Add
T6
T1
Figure7.12.GenerationoftheZincontrolsignalfortheprocessorinFigure7.1.
Generating End
Add
T7
Branch
T5
T4
End
Figure7.13. GenerationoftheEndcontrolsignal.
T5
A Complete Processor
Instruction
unit
Integer
unit
Instruction
cache
Floatingpoint
unit
Data
cache
Businterface
Processor
Systembus
Main
memory
Input/
Output
Figure7.14. Blockdiagramofacompleteprocessor.
Microprogrammed
Control
Overview
Micro
instruction
PCout
MARin
Read
MDRout
IRin
Yin
Select
Add
Zin
Z out
R1out
R1 in
R3out
WMFC
End
Figure7.15 AnexampleofmicroinstructionsforFigure7.6.
Overview
Step A ction
1
MDRout , IR in
R1out , Y in , WMF C
Overview
Control store
IR
Starting
address
generator
Clock
P C
Control
store
One function
cannot be carried
out by this simple
organization.
CW
Figure7.16. Basicorganizationofamicroprogrammedcontrolunit.
Overview
The previous organization cannot handle the situation when the control
unit is required to check the status of the condition codes or external
inputs to choose between alternative courses of action.
Use conditional branch microinstruction.
Address
Microinstruction
0
Zout , PC in , Y in , WMFC
MDRout , IR in
3
Branchto startingaddress
of appropriate
microroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25
26
Offset-field-of-IR
out , SelectY,Add, Zin
27
Zout , PC in , End
Figure 7.17. Microroutine for the instruction Branch<0.
Overview
External
inputs
IR
Startingand
branchaddress
generator
Clock
PC
Control
store
Figure7.18.
Condition
codes
CW
Organizationofthecontrolunittoallow
conditionalbranchinginthemicroprogram.
Microinstructions
A
F2
F3
F4
F5
F1(4bits)
F2(3bits)
F3(3bits)
F4(4bits)
F5(2bits)
0000:Notransfer
0001:PCout
0010:MDRout
0011:Zout
0100:R0out
0101:R1out
0110:R2out
0111:R3out
1010:TEMPout
1011:Offsetout
000:Notransfer
001:PCin
010:IRin
011:Zin
100:R0in
101:R1in
110:R2in
111:R3in
000:Notransfer
001:MARin
010:MDRin
011:TEMPin
100:Yin
0000:Add
0001:Sub
00:Noaction
01:Read
10:Write
F6
F7
1111:XOR
16ALU
functions
F8
F6(1bit)
F7(1bit)
F8(1bit)
0:SelectY
1:Select4
0:Noaction
1:WMFC
0:Continue
1:End
Figure7.19. Anexampleofapartialformatforfieldencodedmicroinstructions.
Further Improvement
Enumerate
Microprogram Sequencing
- Bit-ORing
- Wide-Branch Addressing
- WMFC
Mode
ContentsofIR
OPcode
11 10
Rsrc
8 7
Rdst
4 3
Address
(octal)
Microinstruction
000
PCout,MARin,Read,Select 4 ,Add,Zin
001
Zout,PCin,Yin,WMFC
002
MDRout,IRin
003
Branch{ PC 101(fromInstructiondecoder);
121
122
Zout,Rsrcin
123
170
MDRout,MARin,Read,WMFC
171
MDRout,Yin
172
Rdstout ,SelectY,Add,Z in
173
Zout,Rdstin,End
Figure7.21. MicroinstructionforAdd(Rsrc)+,Rdst.
Note:Microinstructionatlocation170isnotexecutedforthisaddressingmode.
Condition
codes
Decodingcircuits
AR
Controlstore
I R
Nextaddress
Microinstructiondecoder
Controlsignals
Figure7.22.Microinstructionsequencingorganization.
Microinstruction
F0
F0(8bits)
F1
F1(3bits)
F2
F2(3bits)
F4
F5
F6
F3
F3(3bits)
000:Notransfer
001:MARin
010:MDRin
011:TEMPin
100:Yin
F7
F4(4bits)
F5(2bits)
F6(1bit)
F7(1bit)
0000:Add
0001:Sub
00:Noaction
01:Read
10:Write
0:SelectY
1:Select4
0:Noaction
1:WMFC
F9
F10
1111:XOR
F8
F8(1bit)
F9(1bit)
F10(1bit)
0:NextAdrs
1:InstDec
0:Noaction
1:ORmode
0:Noaction
1:ORindsrc
Figure7.23. FormatformicroinstructionsintheexampleofSection7.5.3.
Implementation of the
Microroutine
Octal
address
0
0
0
0
0
0
0
0
0
0
0
0
121
122
0 1 0 1 0 0 1 0 1 0 0 01 1 0 0 1 0 0 0 0 01
0 1 1 1 1 0 0 0 0 1 1 10 0 0 0 0 0 0 0 0 00
1
0
0
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
0
1
1
1
0
0
0
0
1
1
01
00
01
00
00
00
01
10
1
1
0
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F6 F7 F8 F9 F10
0
0
0
0
1
1
1
0
0
0
0
0
F5
0
0
0
1
1
1
1
0
0
0
0
0
F4
0
0
0
1
1
1
1
0
0
0
0
0
F3
0
1
0
0
1
1
1
0
0
0
0
0
F2
1
0
0
0
0
1
2
3
0
0
0
0
F1
01
00
00
00
7
7
7
7
0
1
2
3
F0
0
0
0
0
01
00
00
00
Figure7.24.ImplementationofthemicroroutineofFigure7.21usinga
nextmicroinstructionaddressfield. (SeeFigure7.23forencodedsignals.)
R15in
R15out
R0 in
R0out
Decoder
Decoder
IR
Rsrc
Rdst
InstDecout
External
inputs
Decoding
circuits
Condition
codes
ORmode
ORindsrc
AR
Controlstore
Nextaddress
F1
F2
F8 F9 F10
Rdstout
Rdstin
Rsrcout
Microinstruction
decoder
Rsrcin
Othercontrolsignals
Figure7.25. Somedetailsofthecontrolsignalgeneratingcircuitry.
bit-ORing
Further Discussions
Prefetching
Emulation