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Based Devices
Amitava DasGupta
Department of Electrical Engineering
I.I.T. Madras
Chennai 600037
adg@ee.iitm.ac.in
1
Why SOI ?
CMOS circuits on SOI
has several
advantages resulting
in lower power and
higher speed
Ideal for radiation
hard devices
Ideal substrate for
high temperature
devices, MEMS
based sensors
SOI devices will allow us to keep
up with Moores Law for a longer
2
period
G1
N+
N+
Buried Oxide
Substrate
G2
4
Device performance
Better dielectric isolation in both vertical and horizontal directions
No latch up
Better radiation tolerance
Bulk
Field oxide
Drain
Drain
Buried oxide
Field
Implant
Substrate
Substrate
7
SmartCut process
Hydrogen implantation
through thermal oxide
dose ~1-5e16 cm-2
BOX
B
BOX
BOX
A
H2 peak
At ~400-600C wafer A
separates from B at H2 peak
Handle wafer B
is bonded
A
A
10
SOI-like structures
11
12
Gate oxide
B
Ec
Ec
Ef
Ef
Ev
Ev
C
Ec
Front
gate
oxide
Ef
Ev
Back
gate
oxide
Front
gate
oxide
Back
gate
oxide
Front Inversion
Back Depletion
Front Inversion
Back Inversion
Front Depletion
Back Accumulation
Front Depl.
Back Depl.
Front Depletion
Back Inversion
Front Accumulation
Back Accumulation
Front Accum.
Back Depl.
VG2
Front Accumulation
Back Inversion
14
tOxf
VGf
Front channel
n+
VD
n+
Back channel
tSi
tOxb
VGb
Back Gate
15
00
2B
2B
16
C
C
Q
Vgf VFBf 1 S sf S sb D
Coxf
Coxf
2Coxf
C
C
Q
Vgb VFBb S sf 1 S sb D
Coxb
Coxb
2Coxb
VgbA VFBb
CS
Q
sf D
Coxb
2Coxb
C
VTHA VFBf 1 S
Coxf
sf QD
2Coxf
17
V VFBf
I
Th
C
1 S
Coxf
VgbI VFBb
Hence
sf CS 2 B QD
Coxf
2Coxf
CS
C
Q
sf 1 S 2 B D
Coxb
Coxb
2Coxb
CS
2B
Coxf
C
Vgb VgbA VgbI 1 S 2 B
Coxb
Slope
CS
Coxf
VTh
Vgb
CS
Coxb
C S Coxb
Coxf CS Coxb
Coxb toxf
Coxf toxb
18
Back Accumulation
Model
Measured
Full depletion
Back Inversion
VTHI
0V
VgbA
0.4
VTHF
0.3
-3
Na=4.2e17 cm
TFox=5 nm
TSi=50 nm
VFBF=VFBB=-1 V
0.2
0.1
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
VGB (V)
20
Tb
Gf
D
-2
VGb1
Gb2
Gb3
VGb (V)
-4
VGb1
VGb2
VGb3
-6
-30
-20
-10
10
20
More positive
Transconductance, gm
Gb
V VG f T(Vf (V) )
T h re sh o ld v o ltag e (V )
V =V vs V
Gf Tf
Gb
V =V vs V
VG2
Plateau
More negative
40
50
log I D K
S
S
K
VT ln(10)
2.3VT
1 d log I D
1 d S
S
dVGS
2.3VT dVGS
S 2.3nVT 60n mV
22
n dVGS
control the channel potential?
d S
1 n 1
dVGS
d S
1 n 1
dVGS
23
Coxf
channel
CD
Coxf d VGS S CD d S
C
S 60 1 D
Coxf
mV
CD Citf
S 60 1
Coxf
mV
24
Coxf
Front channel
Cs
Back channel
COXb
Fully Depleted
n1
C
C
S
oxb
S 60 1
Coxf CS Coxb
mV
Assuming CSCD
n 1 FD
n 1 PD
Coxb
1
1
C
CS Coxb 1 S
Coxb
Subthreshold Slope
(mV/dec)
-4
-6 63 mV/dec
-8
102 mV/dec
-10
-12
-15
-0.5
100nm-thic k film
200nm-thic k film
0.0
0.5
1.0
1.5
2.0
120
110
100
90
80
C alculated
Measured
70
60
100
200
300
400
500
Silicon Film Thickness (nm)
600
Current-Voltage relations
SPICE Level-3 model
I D COX
W
1 2
[(VG VTH )VD VD ]
L
2n
1
W
ID
COX (VG VTH ) 2
2n
L
Thin FD SOI
-E
-E
xdmax
Depth in silicon (x)
x1
tsi
28
SOI
Bulk
20
IDsat
A )
30
10
2
3
VG1-VTH (V)
5
29
n+
QB(t)++
n+
ID (mA)
Vg=3.0V
Vg=2.6V
Vg=2.2V
Vg=1.8V
Vg=1.4V
1
0
0
2
VD (V)
3
31
VT VT 0 [ (2 F VSB ) 2 F ]
32
Vout
V(out)
Grounded
2
Floating
Body:
Vin
0
0
V(in)
33
Front gate
Id
Floating
body
Ich
Drain
Vbs
Substrate (back gate)
Cbox
Iii
Increased
drain voltage
c
b
a
0V
Gate Voltage
35
ID (A)
-4
-8
VD=3V
VD=3.3V
VD=3.4V
-12
-16
-2
-1
VG1 (V)
36