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Real Time Operating System

Basic for Developing


Real Time Embedded System

Dania Eridani
dania@ce.undip.ac.id

Teknik Sistem Komputer 2015

Today

Basic architecture
Hardware interfacing
CPU
Memory
I/O

Real Time

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Basic Architecture
Computer CPU and memory connected by bus.
Bus data, address, control

Real time system uniprocessing and multiprocessing


Real time with multiprocessing distributed system or
schedule tasks across the different processor.
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Hardware Interfacing
Latching
A mechanism for recording the appearance of
that signal for later processing.
Ex: interrupt signals are latched into the
programmable interrupt controller so that they
can be serviced at an appropriate time.

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Hardware Interfacing
Edge vs Level Triggered
The signal is represented by the voltage
exceeding a certain threshold.
When the signal reaches that level, an event is
triggered and latched so that another event
cannot be triggered until the latch is reset.

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Hardware Interfacing
Tristate logic
When multiple devices are connected to the same
bus structure it is important that those devices
that are not currently involved in data
interchange remain, essentially, unconnected.
To achieve this effect, those devices that are not
involved are placed into a high-impedance state
at their bus interconnections, that is, they are
tristated .
Hence a particular electrical signal can be in one
of three levels, high, low, or tristated.
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Hardware Interfacing
Wait State
When a microprocessor must interface with a
slower peripheral or memory device, the normal
timing of the microprocessor may need to be
altered.
Specifically, in some cases a wait state may need to
be added to the bus cycles that access that
peripheral or memory.
Wait states extend the microprocessor read or write
cycle by a certain number of processor clock cycles
to allow the device or memory to catch up.

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CPU
The CPU can be thought of as containing several
components connected by its own internal bus,
which is distinct from the memory and address
buses of the system.

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CPU
Fetch and Execute Cycle
Programs are a sequence of macroinstructions or
macrocode. These are stored in the main memory
of the computer in binary form and await
execution.
The macroinstructions are sequentially fetched
from the main memory location pointed to by the
program counter, and placed in the instruction
register.
The control unit decodes the instruction.

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CPU
Microcontroller
Not all real-time systems are based on a
microprocessor.
Some may involve a mainframe or
minicomputers, while others are based on a
microcontroller
A microcontroller is a computer system that is
programmable via microinstructions
Because the complex and time-consuming
macroinstruction decoding process does not
occur, program execution tends to be very fast
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CPU
Instruction Form
An instruction set constitutes the language that
describes a computers functionality.
Instructions in a processor are akin to functions in
procedural programming language in that both
take parameters and return a result.
Most instructions make reference to either
memory locations, pointers to a memory location,
or a register.

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CPU
Pipelining
Pipelining imparts an implicit execution parallelism in the
different cycles of processing an instruction. Suppose
execution of an instruction consists of the following stages:
1. Fetch Get the instruction from memory.
2. Decode Determine what the instruction is.
3. Execute Perform the instruction decode.
4. Write Store the results to memory.
In nonpipelined execution (scalar execution), one
instruction is processed through a cycle at a time.
With pipelining, more instructions can be processed in
different cycles simultaneously, improving processor
performance.
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CPU
Pipelining

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CPU
Core Instruction
There are generally six kinds of instructions. These
can be classified as:
Horizontal-bit operation: The horizontal-bit
operation is a generalization of the fact that these
instructions alter bits within a memory in the
horizontal direction, independent of one another
For example, the third bit in the operands would
affect the third bit in the resultant
Usually, these instructions are the AND, OR,
XOR, NOT operations.
Vertical-bit operation: The vertical-bit operation
alters a bit within a memory word in relation to the
other bits.
These are the
rotate-left,
shift-right,14
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CPU
Core Instruction
There are generally six kinds of instructions. These
can be classified as:
Control: Both horizontal- and vertical-bit operations
can alter a word within a memory location, but a
processor has to alter its state to change flow of
execution and which instructions the processor
executes
Data movement: The I/O movement instructions
are used to move data to and from registers, ports,
and memory
Mathematical/special processing: The bit operation
instructions can create the effects of binary
arithmetic, but it is far more efficient to have the
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logic gates at the machine hardware level

CPU
Core Instruction
There are generally six kinds of instructions. These
can be classified as:
Other (processor specific): The only other kinds of
instructions are those specific to a particular
architecture.
For example, the 8086 LOCK, The 68000 has an
ILLEGAL instruction,
Such instructions as LOCK and ILLEGAL are
highly processor architecture specific, and are
rooted in the design requirements of the
processor.
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CPU
CISC
Complex instruction set computers (CISC) supply
relatively sophisticated functions as part of the
instruction set.
This gives the programmer a variety of powerful
instructions with which to build applications
programs and even more powerful software tools,
such as assemblers and compilers.
In this way, CISC processors seek to reduce the
programmers coding responsibility, increase
execution speeds, and minimize memory usage.
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CPU
RISC
In a reduced instruction set computer (RISC) each
instruction takes only one machine cycle.
Classically, RISCs employ little or no microcode.
This means that the instruction-decode procedure
can be implemented as a fast combinational circuit,
rather than a complicated microprogram scheme.
In addition, reduced chip complexity allows for more
on-chip storage (i.e., general-purpose registers).
Effective use of register direct instructions can
decrease unwanted memory fetch time
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CPU
CISC vs RISC
CISC

RISC

Complex instructions take many Simple instructions taking one


different cycles.
clock cycle.
Any instruction can reference
memory.

LOAD/STORE architecture to
reference memory.

No instructions are pipelined.

Highly pipelined design.

A microprogram is executed for


each native instruction.

Instructions executed directly by


hardware.

Instructions are of variable


format.

Fixed-format instructions.

There are multiple instructions


and addressing modes.

Few instructions and addressing


modes.

There is a single set of


registers.

Large multiple-register sets.

Complexity is in the
Complexity handled by the
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microprogram and hardware.
compiler and software.

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Memory
Memory Access
The typical microprocessor bus read cycle
embodies the handshaking between the
processor and the main memory store.
The time to complete the handshaking is entirely
dependent on the electrical characteristics of the
memory device and the bus

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Memory
Memory technologies
Volatile (the contents will be lost if power is
removed) or non-volatile (the contents are
preserved upon removing power).
Primary and secondary memory storage forms a
hierarchy involving access time, storage density,
cost, and other factors. Clearly, the fastest
possible memory is desired in real-time systems,
but cost control generally dictates that the fastest
affordable technology is used as required.

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Memory
Memory technologies
In order of fastest to slowest, and considering
cost, memory should be assigned as follows:
1. Internal CPU memory
2. Registers
3. Cache
4. Main memory
5. Memory on board external devices

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I/O
In real-time systems the input devices are
sensors, transducers, steering mechanisms, and
so forth.
Output devices are typically actuators, switches,
and display devices.
Input and output are accomplished through one of
three different methods:
programmed I/O,
memory-mapped I/O,
or direct memory address (DMA).

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I/O
Programmed I/O
In programmed I/O, special data-movement instructions
are used to transfer data to and from the CPU.
An IN instruction will transfer data from a specified I/O
device into a specified CPU register.
An OUT instruction will output from a register to some
I/O device.
Normally, the identity of the operative CPU register is
embedded in the instruction code.
Both the IN and OUT instructions require the efforts of
the CPU, and thus cost time that could impact real-time
performance.
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I/O
Direct Memory Access
In DMA, access to the computers memory is
given to other devices in the system without CPU
intervention.
That is, information is deposited directly into main
memory by the external device
Here a DMA controller is
required
unless the DMA circuitry is
integrated into the CPU.
Because CPU participation is
not required, data transfer is
fast.

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I/O
Memory-Mapped I/O
Memory-mapped I/O provides a data-transfer
mechanism that is convenient because it does
not require the use of special CPU I/O instructions.
In memorymapped I/O certain designated
locations of memory appear as virtual I/O ports

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I/O
Interrupt
Software interrupt: from some instruction when
an instruction executed by master processor
Internal hardware interrupt: event from trouble
from some executed instruction like illegal math
operation, debugging, invalid instruction
External hardware interrupt: from hardware
beside master processor, like I/O

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Latihan
1. Apa yang kalian pahami mengenai interrupt?
2. Bagaimana proses penyimpanan data dan
instruction yang ada pada interrupt terkait
dengan latching dan tristate logic?
3. Jelaskan siklus eksekusi yang ada di CPU dan
bandingkan proses eksekusi biasa dengan
proses pipelining.
4. Apa yang kalian pahami tentang DMA?

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Sekian dan Terimakasih . . .

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