Implementation Strategies

ROM-based Design

Example: BCD to Excess 3 Serial Converter

Conversion Process
Bits are presented in bit serial fashion
starting with the least significant bit
Single input X, single output Z

BCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001

Xilinx FPGAs - 1

Excess 3 Code
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100

Implementation Strategies
Present State
S0
S1
S2
S3
S4
S5
S6

Next
X=0
S1
S3
S4
S5
S5
S0
S0

State
X=1
S2
S4
S4
S5
S6
S0
--

Output
X=0 X=1
1
0
1
0
0
1
0
1
1
0
0
1
1
--

State Transition Table

Reset
0/1
S1
0/1

S0

S2

1/0

0/0,
1/1

0/1

S5
0/0,
1/1

Derived State Diagram

S4

S3
0/0,
1/1

1/0

1/0
S6
0/1

Xilinx FPGAs - 2

Implementation Strategies
ROM-based Implementation
ROM Address
X Q2 Q1 Q0
0
0
0 0
0
0
0 1
0
0
1 0
0
0
1 1
0
1
0 0
0
1
0 1
0
1
1 0
0
1
1 1
1
0
0 0
1
0
0 1
1
0
1 0
1
0
1 1
1
1
0 0
1
1
0 1
1
1
1 0
1
1
1 1

ROM Outputs
Z D2 D1 D0
1 0
0 1
1 0
1 1
0 1
0 0
0 1
0 1
1 1
0 1
0 0
0 0
1 0
0 0
X X X X
0 0
1 0
0 1
0 0
1 1
0 0
1 1
0 1
0 1
1 0
1 0
0 0
X X X X
X X X X

1
CLK
1
0

conv erter ROM

Z
X
D2
Q2
D1
Q1
D0
Q0
1
0

9
13
12
5
4

CLK
D
C
B
A

QD
175 QD
QC
QC
QB
QB

1 CLR
\Reset

15
14
10
11
7
6

2
QA
3
QA

Circuit Level Realization

74175 = 4 x positive edge triggered D FFs

Truth Table/ROM I/Os

In ROM-based designs, no need
to consider
state
Xilinx
FPGAs
- 3assignment

Implementation Strategies
LSB

MSB

Timing Behavior for input strings 0 0 0 0 (0) and 1 1 1 0 (7)

0
1

0000
LSB

0
1

0
0

1
0

1100

1
0

1
1

1110
LSB

Xilinx FPGAs - 4

0
0

0101

Implementation Strategies
PLA-based Design
State Assignment with NOVA
0
1
0
1
0
1
0
1
0
1
0
1
0

S0
S0
S1
S1
S2
S2
S3
S3
S4
S4
S5
S5
S6

S1
S2
S3
S4
S4
S4
S5
S5
S5
S6
S0
S0
S0

1
0
1
0
0
1
0
1
1
0
0
1
1

NOVA input file

S0
S1
S2
S3
S4
S5
S6

=
=
=
=
=
=
=

000
001
011
110
100
111
101

NOVA derived
state assignment
9 product term
implementation

Xilinx FPGAs - 5

Implementation Strategies
.i 4
.o 4
.ilb x q2
.ob d2 d1
.p 16
0 000 001
1 000 011
0 001 110
1 001 100
0 011 100
1 011 100
0 110 111
1 110 111
0 100 111
1 100 101
0 111 000
1 111 000
0 101 000
1 101 --0 010 --1 010 --.e

Espresso Inputs
q1 q0
d0 z
1
0
1
0
0
1
0
1
1
0
0
1
1
-

Espresso Outputs

.i 4
.o 4
.ilb x q2 q1 q0
.ob d2 d1 d0 z
.p 9
0001 0100
10-0 0100
01-0 0100
1-1- 0001
-0-1 1000
0-0- 0001
-1-0 1000
--10 0100
---0 0010
.e

Xilinx FPGAs - 6

Implementation Strategies
D2 = Q2 Q0 + Q2 Q0
D1 = X Q2 Q1 Q0 + X Q2 Q0 + X Q2 Q0 + Q1 Q0
D0 = Q0
Z = X Q1 + X Q1
1
CLK 9
1
0

conv erter PLA

X
Q2
Q1
Q0

Z
D2
D1
D0
1
0

13
12
5
4

CLK

175

D
C
B
A

1 CLR
\Reset

15
QD
14
QD
10
QC
11
QC
7
QB
6
QB
2
QA
3
QA

Xilinx FPGAs - 7

Implementation Strategies
10H8 PAL: 10 inputs, 8 outputs, 2 product terms per OR gate
D1 = D11 + D12
D11 = X Q2 Q1 Q0 + X Q2 Q0
D12 = X Q2 Q0 + Q1 Q0
0 1 2 3

0. Q2 Q0
1. Q2 Q0
8. X Q2 Q1 Q0
9. X Q2 Q0
16. X Q2 Q0
17. Q1 Q0
24. D11
25. D12
32. Q0
33. not used
40. X Q1
41. X Q1

45

89

12 13 16 17 20 21 24 25

28 29 30 31

X
0
1

D2

8
9

D11

16
17

D12

24
25

D1

32
33

D0

40
41

Q2

Q1

Q0

D11

D12

Xilinx FPGAs - 8

Implementation Strategies
0 1 2 3

45

89

12 13 16 17 20 21 24 25

28 29 30 31

PAL10H8
X
Q2
Q1
Q0

20

19

3
4

18
17

5
6
7
8
9
10

AND
Gate
Array

D2

8
9

D11

16
17

D12

24
25

D1

32
33

D0

40
41

Q2
D2

Q1

16

D1

15
14

D0
Z

Q0

13
12
11

0
1

D11

D12

Xilinx FPGAs - 9

Implementation Strategies
Buffered Input
or product term

Registered PAL Architecture

CLK

OE

Q2 Q0 + Q2 Q0

Q2 Q0
Q2 Q0

D2

DQ
Q

Q2+

Q2+

Q2+
Q2 Q0 + Q2 Q0

Q2 Q2

Q0 Q0

Negative Logic
Feedback
D1 = X Q2 Q1 Q0 + X Q2 + X Q0 + Q2 Q0 + Q1 Q0
D2 = Q2 Q0 + Q2 Q0

D0 = Q0
Z = X Q1 + X Q1

Xilinx FPGAs - 10

Implementation Strategies
Programmable Output Polarity/XOR PALs
CLK

OE

Buried Registers: decouple

FF from the output pin

DQ
Q

Advantage of XOR PALs: Parity and Arithmetic Operations

A
A
A
A
A
A
A
A

B
B
B
B
B
B
B
B

C
C
C
C
C
C
C
C

D
D
D
D
D
D
D
D

A B C D

AB
AB
CD
CD

Xilinx FPGAs - 11

A B C D

Implementation Strategies
Example of XOR PAL

Example of Registered PAL

INC REMEN
T

INCREMEN
T

1
FIRST
FUSE
N UMBER

0
40

12

16

20

24

28

32

36
D

80
120

23

FIR ST
FUSE
NU MBER
S

0
32
64
96
128
160
192
224

12

16

20

24

28

19

2
160
200

240
280

22

256
288
320
352
384
416
448
480

Q
3
320
360

400
440

21

560
600

20

720
760

18

512
544
576
608
640
672
704
736

768
800
832
864
896
928
960
992

17

Q
5
640
680

480
520

19

16

5
6
800
840

880
920

1024
1056
1088
1120
1152
1184
1216
1248

18

Q
7

15

6
960
1000

1040
1080

17

1280
1312
1344
1376
1408
1440
1472
1504

Q
8
1120
1160

1200
1240

16

1536
1568
1600
1632
1664
1696
1728
1760

1360
1400

15

1520
1560

1792
1824
1856
1888
1920
1952
1984
2016

14

Q
13

11
INCR EMEN
T

12

16

20

24

28

NOTE: FUSE NUMBER = FIRST FUSE NU MBER +

INCR EMENT

32

36

14

13

Q
10
1440
1480

1280
1320

Xilinx FPGAs - 12

12

11

Specifying PALs with ABEL

P10H8 PAL

module bcd2excess3
title 'BCD to Excess 3 Code Converter State Machine'
u1 device 'p10h8';
"Input Pins
X,Q2,Q1,Q0,D11i,D12i

pin

1,2,3,4,5,6;

"Output Pins
D2,D11o,D12o,D1,D0,Z

pin

19,18,17,16,15,14;

INSTATE = [Q2, Q1, Q0];

S0 = [0, 0, 0];
S1 = [0, 0, 1];
S2 = [0, 1, 1];
S3 = [1, 1, 0];
S4 = [1, 0, 0];
S5 = [1, 1, 1];
S6 = [1, 0, 1];

Explicit equations
for partitioned
output functions

equations
D2 = (!Q2 & Q0) # (Q2 & !Q0);
D1 = D11i # D12i;
D11o = (!X & !Q2 & !Q1 & Q0) # (X & !Q2 & !Q0);
D12o = (!X & Q2 & !Q0) # (Q1 & !Q0);
D0 = !Q0;
Z = (X & Q1) # (!X & !Q1);
end bcd2excess3;

Xilinx FPGAs - 13

Specifying PALs with ABEL

P12H6 PAL

module bcd2excess3
title 'BCD to Excess 3 Code Converter State Machine'
u1 device 'p12h6';
"Input Pins
X, Q2, Q1, Q0

pin

1, 2, 3, 4;

"Output Pins
D2, D1, D0, Z

pin

17, 18, 16, 15;

INSTATE = [Q2, Q1,

S0in = [0, 0, 0];
S1in = [0, 0, 1];
S2in = [0, 1, 1];
S3in = [1, 1, 0];
S4in = [1, 0, 0];
S5in = [1, 1, 1];
S6in = [1, 0, 1];

Simpler equations

Q0]; OUTSTATE = [D2, D1, D0];

S0out = [0, 0, 0];
S1out = [0, 0, 1];
S2out = [0, 1, 1];
S3out = [1, 1, 0];
S4out = [1, 0, 0];
S5out = [1, 1, 1];
S6out = [1, 0, 1];

equations
D2 = (!Q2 & Q0) # (Q2 & !Q0);
D1 = (!X & !Q2 & !Q1 & Q0) # (X & !Q2 & !Q0) #
(!X & Q2 & !Q0) # (Q1 & !Q0);
D0 = !Q0;
Z = (X & Q1) # (!X & !Q1);
end bcd2excess3;

Xilinx FPGAs - 14

Specifying PALs with ABEL

P16R4 PAL
module bcd2excess3
title 'BCD to Excess 3 Code Converter'
u1 device 'p16r4';
"Input Pins
Clk, Reset, X, !OE
"Output Pins
D2, D1, D0, Z
SREG
S0 =
S1 =
S2 =
S3 =
S4 =
S5 =
S6 =

= [D2,
[0, 0,
[0, 0,
[0, 1,
[1, 1,
[1, 0,
[1, 1,
[1, 0,

pin

1, 2, 3, 11;

pin 14, 15, 16, 13;

D1, D0];
0];
1];
1];
0];
0];
1];
1];

state_diagram SREG
state S0: if Reset then S0
else if X then S2 with Z = 0
else S1 with Z = 1
state S1: if Reset then S0
else if X then S4 with Z = 0
else S3 with Z = 1
state S2: if Reset then S0
else if X then S4 with Z = 1
else S4 with Z = 0
state S3: if Reset then S0
else if X then S5 with Z = 1
else S5 with Z = 0
state S4: if Reset then S0
else if X then S6 with Z = 0
else S5 with Z = 1
state S5: if Reset then S0
else if X then S0 with Z = 1
else S0 with Z = 0
state S6: if Reset then S0
else if !X then S0 with Z = 1
end bcd2excess3;

Xilinx FPGAs - 15

FSM Design with Counters

Synchronous Counters: CLR, LD, CNT

Four kinds of transitions for each state:

(1) to State 0 (CLR)
(2) to next state in sequence (CNT)
(3) to arbitrary next state (LD)
(4) loop in current state

CLR
CNT
n+1

no
signals
asserted
LD
m

Careful
Carefulstate
stateassignment
assignmentisisneeded
neededto
toreflect
reflectbasic
basicsequencing
sequencing
of
the
counter
of the counter

Xilinx FPGAs - 16

FSM Design with Counters

Excess 3 Converter Revisited
Reset
0/1
1
0/1

1/0

0/0,
1/1

0/0,
1/1

0/1

Note the sequential nature

of the state assignments

2
0/0,
1/1

1/0

1/0
6
0/1

Xilinx FPGAs - 17

FSM Design with Counters

Excess 3 Converter
Inputs/Current
Next
Outputs
State
State
X Q2 Q1 Q0 Q2+ Q1+ Q0+ Z CLR LD EN
0 0 0 0
0
0
1
1 1 1 1
0 0 0 1
0
1
0
1 1 1 1
0 0 1 0
0
1
1
0 1 1 1
0 0 1 1
0
0
0
0 0 X X
0 1 0 0
1
0
1
1 1 1 1
0 1 0 1
0
1
1
0 1 0 X
0 1 1 0
0
0
0
1 0 X X
0 1 1 1
X
X
X X X X X
1 0 0 0
1
0
0
0 1 0 X
1 0 0 1
1
0
1
0 1 0 X
1 0 1 0
0
1
1
1 1 1 1
1 0 1 1
0
0
0
1 0 X X
1 1 0 0
1
0
1
0 1 1 1
1 1 0 1
1
1
0
1 1 1 1
1 1 1 0
X
X
X X X X X
1 1 1 1
X
X
X X X X X

C
X
X
X
X
X
0
X
X
1
1
X
X
X
X
X
X

B
X
X
X
X
X
1
X
X
0
0
X
X
X
X
X
X

A
X
X
X
X
X
0
X
X
0
1
X
X
X
X
X
X

CLR signal dominates LD which dominates Count

Xilinx FPGAs - 18

Implementing FSMs with

Counters
.i 5
Espresso Input File .i 5
.o 7
.o 7
.ilb res x q2 q1 q0
.ilb res x q2 q1 q0
.ob z clr ld en c b a
.ob z clr ld en c b a
.p 17
.p 10
1---- -0----0-001 0101101
00000 1111---0-01 1000000
00001 1111---11-0 1000000
00010 0111--0-0-0 0101100
00011 00-----000- 1010000
Excess
3
Converter
00100 0111---0--0 0010000
00101 110-011
0-10- 0101011
00110 10------11- 1000000
00111 -------11-- 0010000
01000 010-100
-1-1- 1010000
01001 010-101
.e
01010 1111--01011 10----Espresso Output File
01100 1111--01101 0111--01110 ------01111 ------Xilinx FPGAs - 19
.e

FSM Implementation with Counters

CLK
1
0
1
0

excess 3 PLA
X

Reset
X
Q2
Q1
Q0

Z
\CLR
\LD
EN
C
B
A

7
P
10
163
T
RCO15
2
CLK
6 D
QD 11
5 C
QC 12
4 B
QB 13
3 A
14
QA
9 LOAD
1

CLR

Excess 3 Converter Schematic

Synchronous Output Register

Xilinx FPGAs - 20

D Q
C Q

Implementation Strategies
Xilinx LCA Architecture
Implementing the BCD to Excess 3 FSM
Q2+ = Q2 Q0 + Q2 Q0
Q1+ = X Q2 Q1 Q0 + X Q2 Q0 + X Q2 Q0 + Q1 Q0
Q0+ = Q0
Z = Z Q1 + X Q1
No function more complex than 4 variables
4 FFs implies 2 CLBs
Synchronous Mealy Machine
Global Reset to be used
Place Q2+, Q0+ in once CLB
Q1, Z in second CLB
maximize use of direct & general purpose interconnections

Xilinx FPGAs - 21

Implementing the BCD to Excess 3 FSM

Clk

Clk

CE
CE

CE

DI
B

X
Q2
Q0

FG

Q2

B
C

C
Y
K

Q0

DI

FG

Q0

A
X

X
Q2
Q1
Q0

FG

X
Q1

FG

E
D

RES

RES

CLB2

CLB1

Xilinx FPGAs - 22

Q1

Design Case Study

Traffic Light Controller

Decomposition into primitive subsystems

Controller FSM
next state/output functions
state register
Short time/long time interval counter
Car Sensor
Output Decoders and Traffic Lights

Xilinx FPGAs - 23

Design Case Study

Traffic Light Controller
Block Diagram

Re s e t
Clk
TS

s hort tim e /
long tim e
counter
TL

Clk

controlle r fs m

Re s et
C (as ync)

ST
Next State 2
Output
2
Logic

Car
Se ns or C (sync)

Encode d
Light
Light
De code rs
Signals

2
2

State
Re gis ter

Xilinx FPGAs - 24

3
3
H

Design Case Study

0

Subsystem Logic
Present

Light
Decoders

F0

2 A
3 B

F1

1 G

RQ
\Present

Y0
Y1
Y2
Y3

139a

\Reset

4
5
6
7
1

H0

CLK

Interval
Timer

CLK

Reset
ST

H1
+

7 P
10 T 163
1
2 CLK RCO
5
6 D
QD 11
5 C
QC 12
4 B
QB 13
3 A
QA 14
9 LOAD

CLR 1

CLR

HG HY HR

Car Detector

FG FY FR

+
Cin

1 A
Y0
1
4 B
Y1
3
Y2
1 G
Y3
5
139b
TL

Xilinx FPGAs - 25

TS

1
1
2
1
09

Design Case Study

State Assignment: HG = 00, HY = 10, FG = 01, FY = 11
P1 = C TL Q1 + TS Q1 Q0 + C Q1 Q0 + TS Q1 Q0
P0 = TS Q1 Q0 + Q1 Q0 + TS Q1 Q0
ST = C TL Q1 + C Q1 Q0 + TS Q1 Q0 + TS Q1 Q0
HL[1] = TS Q1 Q0 + Q1 Q0 + TS Q1 Q0
HL[0] = TS Q1 Q0 + TS Q1 Q0

Next State Logic

FL[1] = Q0
FL[0] = TS Q1 Q0 + TS Q1 Q0
PAL/PLA Implementation:
5 inputs, 7 outputs, 8 product terms
PAL 22V10 -- 11 inputs, 10 prog. IOs, 8 to 14 prod terms per OR
ROM Implementation:
32 word by 8-bit ROM (256 bits)
Xilinx FPGAs
Reset may double ROM size

- 26

Design Case Study

Counter-based Implementation
HG
TLC / ST
HY
TS / ST
FG
TL+C / ST

TS
TL
\C
TL
C

1 GA
3 A3
4 A2
5 A1
6 A0
13
12
11
10
15

B3
B2
B1
B0
GB

2 x 4:1 MUX

153
YA 7

YB 9

S1 SO
2 14

ST

7
10 P 163
T
15
2 CLK RCO
6
5
4
3

D
C
B
A

QD
QC
QB
QA

11
12
13
14

9 LOAD
\Reset 1 CLR

FY
TS / ST

ST = Count

TTL Implementation with MUX and Counter

Can we reduce package count by using an 8:1 MUX?

Xilinx FPGAs - 27

Q1
Q0

Design Case Study

Counter-based Implementation

Dispense with direct output functions for the traffic lights

Why not simply decode from the current state?
HG HY HR
1
1 G

Q1
Q0

3B
2A

Y3
Y2
Y1
Y0

7
6
5
4

139a

ST is a Synchronous Mealy Output

Light Controllers are Moore Outputs

Xilinx FPGAs - 28

FG FY FR
0

Design Case Study

LCA-Based Implementation
Discrete Gate Method:
None of the functions exceed 5 variables
P1, ST are 5 variable (1 CLB each)
P0, HL1, HL0, FL0 are 3 variable (1/2 CLB each)
FL1 is 1 variable (1/2 CLB)
4 1/2 CLBs total!

Xilinx FPGAs - 29

Design Case Study

TL C TS

TS

TS

LCA-Based
Implementation
Placement of
functions selected
to maximize the
use of direct
connections

Q0

DI CE A
B
X
C F0
K
Y
E D R

TL

DI CE A
B
X
C
K
Y
E D R

DI CE A
B
X
C Q1
K
Y
E D R

Q1
TS

Q0
DI CE A
B
X
C
K
Y
E D R

Q1
TL
TS
C
Q0

F1
Q0

Q1

Q0
TS

Q1

DI CE A
B
X
C ST
K
Y
E D R

Xilinx FPGAs - 30

DI CE A
B
X
C
K
Y
E D R

H1
H0

Design Case Study

LCA-Based Implementation
Counter/Multiplexer Method:

4:1 MUX, 2 Bit Upcounter

MUX: six variables (4 data, 2 control)
but this is the kind of 6 variable function that can be
implemented in 1 CLB!
2nd CLB to implement TL C and TL + C'
But note that ST/Cnt is really a function of TL, C, TS, Q1, Q0
1 CLB to implement this function of 5 variables!
2 Bit Counter: 2 functions of 3 variables (2 bit state + count)
Also implemented in one CLB
Traffic light decoders: functions of 2 variables (Q1, Q0)
2 per CLB = 3 CLB for the six lights
Total count = 5 CLBs

Xilinx FPGAs - 31