LPD 3 4 CMOSPower

CSV881: Low-Power Design
Power Dissipation in CMOS Circuits

Vishwani D. Agrawal
James J. Danaher Professor

Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
nMOS Logic (Inverters)

For logic 1 input,
continuous static
power is dissipated.
Pseudo-nMOS
Saturated-load nMOS
R. C. Jaeger and T. N. Blalock, Microelctronic Circuit Design,

Third Edition, McGraw-Hill, 2006, Chapter 6.
CMOS Logic (Inverter)

VDD
No current flows
from power supply!
Where is power
consumed?
GND
F. M. Wanlass and C. T. Sah, Nanowatt Logic using Field-Effect

Metal-Oxide-Semiconductor Triodes, IEEE International SolidState Circuits Conference Digest, vol. IV, February 1963, pp.
32-33.
Components of Power
Dynamic
Signal
transitions
Logic
activity
Glitches
Short-circuit
Static
Leakage
(small)
Ptotal =
=
Pdyn + Pstat
Ptran + Psc + Pstat
4
Power of a Transition: Ptran

V = VDD
R = Ron
i(t)
vi (t)
Large
resistance
v(t)
C = CL
Ground
C =
Total load capacitance for gate; includes transistor capacitances

of driving gate + routing capacitance + transistor capacitances
of driven gates; obtained by layout analysis.
Charging of a Capacitor
R
t=0
i(t)
v(t)
C
Charge on capacitor, q(t)
C v(t)
Current, i(t)
C dv(t)/dt
dq(t)/dt
i(t)
C dv(t)/dt =
[V v(t)] /R
dv(t)
=
dt
dv(t)
=
V v(t)
V v(t)
RC
dt

RC
t
ln [V v(t)]
=
+ A
RC
Initial condition, t = 0, v(t) = 0 A = ln V
v(t) =
V [1
exp()]
t
RC
v(t) =
i(t)
t
V [1 exp( )]
RC
dv(t)
C
dt
V
t
exp( )
R
RC
Total Energy Per Charging Transition

from Power Supply
Etrans =
dt
=
V i(t) dt =
V
t
exp( )
CV
RC
Energy Dissipated per Transition in

Resistance
2
R i (t) dt
dt
V
2t
R exp( )
R2 0
RC
1
2
CV
2
10
Energy Stored in Charged Capacitor
t V
t
v(t) i(t) dt = V [1-exp( )] exp( ) dt
0
0
RC R
RC
1
2
= CV
2
11
Transition Power
Gate
output rising transition
Energy
dissipated in pMOS transistor = CV2/2

Energy stored in capacitor = CV2/2
Gate
output falling transition
Energy
dissipated in nMOS transistor = CV2/2
Energy
dissipated per transition = CV2/2

Power dissipation:
Ptrans =
fck
Etrans fck =
fck CV /2
=
activity factor
=
clock frequency
12
Components of Power
Dynamic
Signal
transitions
activity
Glitches
Static
Leakage
2
Delay
=1
Logic
Short-circuit
GLITCH
Delay=2
Ptotal =
=
Pdyn + Pstat
Ptran + Psc + Pstat
13
Short Circuit Power of a Transition: Psc

VDD
vi (t)
isc(t)
vo(t)
CL
Ground
14
Short Circuit Current, isc (t)

VDD
VDD - VTp
Vi (t)
Volt
ptransistor
starts
conducting
Vo(t)
VTn
Iscmaxf
isc(t)
Isc
0
n-transistor
cuts-of
tB
tE
Time (ns)
15
Peak Short Circuit Current

Increases
with the size (or gain, ) of

transistors
Decreases with load capacitance, CL
Largest
when CL = 0
Reference: M. A. Ortega and J. Figueras,
Short Circuit Power Modeling in Submicron
CMOS, PATMOS 96, Aug. 1996, pp. 147166.
16
Short-Circuit Energy per Transition

Escf
tBtE VDD isc(t)dt
= (tE tB) Iscmaxf VDD / 2

Escf
tf (VDD - |VTp| - VTn) Iscmaxf / 2
Escr
tr (VDD - |VTp| - VTn) Iscmaxr / 2
Escf
= Escr = 0, when VDD = |VTp| + VTn
17
Short-Circuit Power
Increases
with rise and fall times of input.

Decreases for larger output load
capacitance; large capacitor takes most of
the current.
Small, about 5-10% of dynamic power;
momentary shorting of supply and ground
during opening and closing of transistor
switches.
18
Short-Circuit Power Calculation

Assume
equal rise and fall times

Model input-output capacitive coupling
(Miller capacitance)
Use a spice model for transistors
T. Sakurai
and A. Newton, Alpha-power Law

MOSFET model and Its Application to a
CMOS Inverter, IEEE J. Solid State Circuits,
vol. 25, April 1990, pp. 584-594.
19
Short Circuit Power
Psc
fck Esc
20
Psc, Rise Time and Capacitance

Ron
vi (t)
VDD
VDD
ic(t)+isc(t)
vo(t)
vo(t)
tf
CL
R = large
tr
Ground
vo(t)
R
21
isc, Rise Time and Capacitance
Isc(t) =
t
VDD[1 exp ()]
vo(t)
R(t) C
=
R(t)
R(t)
22
iscmax, Rise Time and Capacitance

i
Small C
vo(t)
Large C
vo(t)
iscmax
R(t)
tf
t
23
Psc, Rise Times, Capacitance

For
given input rise and fall times short

circuit power decreases as output
capacitance increases.
Short circuit power increases with increase
of input rise and fall times.
Short circuit power is reduced if output rise
and fall times are longer than the input rise
and fall times.
24
Summary: Short-Circuit Power

Short-circuit
power is consumed by each

transition (increases with input transition time).
Reduction requires that gate output transition
should not be faster than the input transition
(faster gates can consume more short-circuit
power).
Increasing the output load capacitance reduces
short-circuit power.
Scaling down of supply voltage with respect to
threshold voltages reduces short-circuit power;
completely eliminated when VDD |Vtp| + Vtn .
25
Components of Power
Dynamic
Signal
transitions
Logic
activity
Glitches
Short-circuit
Static
Leakage
26
Leakage Power
Ground
Gate
IG
VDD
R
Source
Drain
n+
Bulk Si (p)
Isub
IPT
IGIDL
n+
ID
nMOS Transistor
27
Leakage Current Components

Subthreshold
Reverse
conduction, Isub
bias pn junction conduction, ID
Gate
induced drain leakage, IGIDL due to

tunneling at the gate-drain overlap
Drain source punchthrough, IPT due to short
channel and high drain-source voltage
Gate tunneling, IG through thin oxide; may
become significant with scaling
28
Drain to Source Current

IDS = 0 Cox (W/L) Vt2 exp{(VGS VTH ) / nVt }
0: carrier surface mobility
Cox: gate oxide capacitance per unit area
L: channel length
W: gate width
Vt = kT/q: thermal voltage
n: a technology parameter
29
IDS for Short Channel Device

IDS= 0 Cox(W/L)Vt2 exp{(VGS VTH + VDS)/nVt}
VDS = drain to source voltage
: a proportionality factor
W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submic

Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp. 81-104
30
Subthreshold Current, Isub

Example:
90nm CMOS inverter
L =
90nm, Wp = 495nm, Wn = 216nm

Temperature 300K (room temperature)
Input set to 0 volt
Vthn = 0.291V, Vthp =0.209V at VDD = 1.2V (nominal)
PTM (predictive technology model)
Spice simulation for leakage current
31
32
33
Increased Subthreshold Leakage
Log (Drain current)
Scaled device
Ic
Isub
0 VTH VTH
Gate voltage
34
Summary: Leakage Power

Leakage
power as a fraction of the total power

increases as clock frequency drops. Turning
supply off in unused parts can save power.
For a gate it is a small fraction of the total power; it
can be significant for very large circuits.
Scaling down features requires lowering the
threshold voltage, which increases leakage power;
roughly doubles with each shrinking.
Multiple-threshold devices are used to reduce
leakage power.
35
CMOS Gate Power

R = Ron
V
i(t)
vi (t)
Large
resistance
v(t)
v(t)
C
isc(t)
i(t)
isc(t)
Ground
Leakage
current
time
36
Technology Scaling
Scaling
down 0.7 micron by factors 2 and

4 leads to 0.35 and 0.17 micron
technologies
Constant electric field assumed
37
Constant Electric Field Scaling

B.
Davari, R. H. Dennard and G. G.

Shahidi, CMOS Scaling for High
Performance and Low PowerThe Next
Ten Years, Proc. IEEE, April 1995, pp.
595-606.
Other forms of scaling are referred to as
constant-voltage and quasi-constantvoltage.
38
Bulk nMOSFET
Polysilicon
Gate
W
Source
Drain
n+
n+
L
p-type body (bulk)
SiO2
Thickness = tox
39
Technology Scaling
A scaling
factor (S ) reduces device dimensions as
1/S.
Successive generations of technology have used a
scaling S = 2, doubling the number of transistors
per unit area. This produced 0.25, 0.18, 0.13,
90nm and 65nm technologies, continuing on to
45nm, 32nm and 22nm.
A 5% gate shrink (S = 1.05) is commonly applied to
boost speed as the process matures.
N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Bosto

Pearson Addison-Wesley, 2005, Section 4.9.1.
40
Constant Electric Field Scaling

Device Parameter
Scaling
Length, L
1/S
Width, W
1/S
Gate oxide thickness, tox
1/S
Supply voltage, VDD
1/S
Threshold voltages, Vtn, Vtp
1/S
Substrate doping, NA
S
41
Constant Electric Field Scaling(Cont.)

Device Characteristic
Scaling
W / (L tox)
(VDD Vt ) 2
1/S
Resistance, R
VDD / Ids
Gate capacitance, C
W L / tox
1/S
Gate delay,
RC
1/S
Clock frequency, f
1/
CV 2 f
1/S 2
Current, Ids
Dynamic power per gate, P

Chip area, A
1/S 2
Power density
P/A
Current density
Ids /A
42
Problem: A Design Example
A battery-operated 65nm digital CMOS device is found

to consume equal amounts (P ) of dynamic power and
leakage power. The short-circuit power is negligible.
The energy consumed by a computing task, that takes
T seconds, is 2PT.
Compare two power reduction strategies for extending
the battery life:
A.
B.
Clock frequency is reduced to half, keeping all other

parameters constant.
Supply voltage is reduced to half. This slows the gates down
and forces the clock frequency to be lowered to half of its
original (full voltage) value. Assume that leakage current is
reduced by a ratio 10/2 = 5 (see slides 32 and 33).
43
Solution: Strategy A. Clock

Frequency Reduction
Reducing the clock frequency will reduce

dynamic power to P / 2, keep the static
power the same as P, and double the
execution time of the task.
Energy consumption for the task will be,
Energy = (P / 2 + P ) 2T = 3PT
which is greater than the original 2PT.
44
Solution: Part B. Supply Voltage

Reduction
When the supply voltage and clock frequency

are reduced to half their values, dynamic power
is reduced to P / 8 and static power to P / 10.
The time of task is doubled and the total energy
consumption is,
Energy = (P / 8 + P / 10) 2T = 9PT / 20 =0.45PT
The voltage reduction strategy reduces energy
consumption while a simple frequency reduction
consumes more energy.
45
Comparing Strategies A and B

Original
Voltage
V/2
Clock Frequency
F/2
F/2
Task Duration
2T
2T
Power
2P
1.5P
0.225P
Energy
2PT
3PT
0.45PT
46

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CSV881: Low-Power Design

Power Dissipation in CMOS Circuits

James J. Danaher Professor

Lectures 3, 4: CMOS Circuits

nMOS Logic (Inverters)

R. C. Jaeger and T. N. Blalock, Microelctronic Circuit Design,

Lectures 3, 4: CMOS Circuits

CMOS Logic (Inverter)

F. M. Wanlass and C. T. Sah, Nanowatt Logic using Field-Effect

Lectures 3, 4: CMOS Circuits

Copyright Agrawal, 2011

Lectures 3, 4: CMOS Circuits

Power of a Transition: Ptran

Total load capacitance for gate; includes transistor capacitances

Copyright Agrawal, 2011

Lectures 3, 4: CMOS Circuits

Charge on capacitor, q(t)

Copyright Agrawal, 2011

Copyright Agrawal, 2011

Lectures 3, 4: CMOS Circuits

Copyright Agrawal, 2011

Lectures 3, 4: CMOS Circuits

Total Energy Per Charging Transition

Copyright Agrawal, 2011

Lectures 3, 4: CMOS Circuits

Energy Dissipated per Transition in

Copyright Agrawal, 2011

Lectures 3, 4: CMOS Circuits

Energy Stored in Charged Capacitor

Copyright Agrawal, 2011

Lectures 3, 4: CMOS Circuits

output rising transition

dissipated in pMOS transistor = CV2/2

output falling transition

dissipated in nMOS transistor = CV2/2

dissipated per transition = CV2/2

Copyright Agrawal, 2011

Lectures 3, 4: CMOS Circuits

Short Circuit Power of a Transition: Psc

Copyright Agrawal, 2011

Lectures 3, 4: CMOS Circuits

Short Circuit Current, isc (t)

Copyright Agrawal, 2011

Peak Short Circuit Current

with the size (or gain, ) of

Lectures 3, 4: CMOS Circuits

Short-Circuit Energy per Transition

tBtE VDD isc(t)dt

= (tE tB) Iscmaxf VDD / 2

tf (VDD - |VTp| - VTn) Iscmaxf / 2

tr (VDD - |VTp| - VTn) Iscmaxr / 2

= Escr = 0, when VDD = |VTp| + VTn

Copyright Agrawal, 2011

Lectures 3, 4: CMOS Circuits

with rise and fall times of input.

Lectures 3, 4: CMOS Circuits

Short-Circuit Power Calculation

equal rise and fall times

and A. Newton, Alpha-power Law

Copyright Agrawal, 2011

Lectures 3, 4: CMOS Circuits

Short Circuit Power

Copyright Agrawal, 2011