Synchronous

sequential logics

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Synchronous sequential logic

Key concepts and Overview

multivibrator
Signal edge
Synchronous sequential logic
Flip flop
S-R latch
S-R -NAND latch
Jk latch
Gated SR latch
D-flipflop

SYNCHRONOUS SEQUENTIAL
LOGIC
There are two types of sequential circuits:
synchronous: outputs change only at specific time
asynchronous: outputs change at any time use (multivibrator )

A multivibrator is an electronic circuit used to implement a

variety of simple two-state systems such as oscillators, timers
and flip-flops. It is characterized by two amplifying devices
(transistors, electron tubes or other devices) cross-coupled by
resistors or capacitors.
Multivibrator: a class of sequential circuits. They can be:
bistable(2 stable states)
monostableor one-shot(1 stable state)
astable(no stable state)
Bistable logic devices: latchesand flip-flops.
Latches and flip-flops differ in the method used for changing their state.

SEQUENTIAL CIRCUIT
The current Intel Pentium IV processors have 55 million
transistors!
A flip-flop holds a single bit of memory
The bit flip-flops between the two NAND gates
In reality, flip-flops are a bit more complicated
Have 5 (or so) logic gates (transistors) per flip-flop
Consider a 1 Gb memory chip
1 Gb = 8,589,934,592 bits of memory
Thats about 43 million transistors!
In reality, those transistors are split into 9 ICs of
about 5 million transistors each

SIGNAL EDGE
IN ELECTRONICS, A SIGNAL EDGE IS A TRANSITION IN A DIGITAL SIGNAL EITHER
FROM LOW TO HIGH (0 TO 1) OR FROM HIGH TO LOW (1 TO 0). IT IS CALLED AN
"EDGE" BECAUSE THE SQUARE WAVE WHICH REPRESENTS A SIGNAL HAS EDGES
AT THOSE POINTS.
A rising edge is the transition from low to high. It is also named positive edge.
When a circuit is rising edge-triggered, it becomes active when its clock signal
goes from low to high, and ignores the high-to-low transition.
A falling edge is the high to low transition. It is also known as the negative edge.
When a circuit is falling edge-triggered, it becomes active when the clock signal
goes from high to low, and ignores the low-to-high transition.
A leading edge is an event that is triggered on the front edge of a pulse. Assuming
a clock begins at t = 0, the first position would be triggered at t = 1.
A trailing edge is the opposite of a leading edge. It is triggered on the back edge
of a pulse. Assuming the clock begins at t = 0, the first position would be triggered
at t = 0.
The terms front edge or leading edge, and back edge or trailing edge describe the
related position of edges in a clock cycle. A leading edge can be a falling edge.

SYNCHRONOUS SEQUENTIAL
LOGIC

Latches and flip-flops (FFs) are the basic building

blocks of sequential circuits
Latches :bistable memory device with level sensitive
triggering (no clock), watches all of its inputs
continuously and changes its outputs, independent of
a clocking signal.
Or

a latch is a device that after taking a single input for say 1 they set their
output to 1 and hold its state until it resets

flip-flop: bistable memory device with edgetriggering (with clock), samples its inputs, and
changes its output only at times determined by a
clocking signal.
Or

Flip flop
Flip flop is a sequential circuit which generally
samples its inputs and changes its outputs only at
particular instants of time and not continuously. Flip
flop is said to be edge sensitive or edge triggered
rather than being level triggered like latches.
Flip-flops can be divided into common types:
the SR ("set-reset")
D ("data" or "delay"[11])
T ("toggle")
JK types are the common ones

S-R latch
S and R stand for set and reset. It can be constructed from a pair of cross-coupled
NOR logic gates. The stored bit is present on the output marked Q.
While the S and R inputs are both low, feedback maintains the Q and Q outputs in
a constant state, with Q the complement of Q. If S (Set) is pulsed high while R
(Reset) is held low, then the Q output is forced high, and stays high when S
returns to low; similarly, if R is pulsed high while S is held low, then the Q output is
forced low, and stays low when R returns to low.
The R = S = 1 combination is called a restricted combination or a forbidden state
because, as both NOR gates then output zeros, it breaks the logical equation Q =
not Q. The combination is also inappropriate in circuits where both inputs may go
low simultaneously (i.e. a transition from restricted to keep). The output would
lock at either 1 or 0 depending on the propagation time relations between the
gates (a race condition).

S-R -NAND latch :It is basically S-R latch using NAND gates with
an additional enable input. It is also called as level triggered SR-FF. For
this circuit in output will take place if and only if the enable input (E) is
made active. In short this circuit will operate as an S-R latch if E= 1 but
there is no change in the output if E = 0.
While the S and R inputs are both low, feedback maintains the Q and Q outputs in
a constant state, with Q the complement of Q. If S (Set) is pulsed high while R
(Reset) is held low, then the Q output is forced high, and stays high when S
returns to low; similarly, if R is pulsed high while S is held low, then the Q output is
forced low, and stays low when R returns to low.

OPERATION

JK latch
The JK latch is much less frequently used than theJK flip-flop. The JK latch follows
the following state table:
JK latch truth table
Hence, the JK latch is an SR latch that is
made totoggleits output (oscillate
Commen
Q
J
K
next
between 0 and 1) when passed the input
t
combination of 11.Unlike the JK flip-flop,
No
the 11 input combination for the JK latch
0 is
0
Q
change
not very useful because there is no clock
that directs toggling.
0
1
0
Reset

1
1
Q
Gated latches and conditional
transparency

Set
Toggle

Latches are designed to be transparent. That is, input signal changes cause
immediate changes in output; when several transparent latches follow each other,
using the same enable signal, signals can propagate through all of them at once.
Alternatively, additional logic can be added to a simple transparent latch to make
it non-transparent or opaque

Gated SR latch
A synchronous SR latch (sometimes clocked SR flip-flop) can be made by adding a second
level of NAND gates to the inverted SR latch (or a second level of AND gates to the direct SR
latch). The extra NAND gates further invert the inputs so the simple SR latch becomes a
gated SR latch (and a simple SR latch would transform into a gated SR latch with inverted
enable).
With E high (enable true), the signals can pass through the input gates to the encapsulated
latch; all signal combinations except for (0,0) = hold then immediately reproduce on the (Q,Q)
output, i.e. the latch is transparent.
With E low (enable false) the latch is closed (opaque) and remains in the state it was left the
last time E was high.
The enable input is sometimes a clock signal, but more often a read or write strobe
.

No action (keep state)

The same as non-clocked SR

latch

D flip-flop The d-ff captures the value of the D-input at a definite portion of the clock
cycle (such as the rising edge of the clock). That captured value becomes the Q output. At
other times, the output Q does not change
Most D-type flip-flops in ICs have the capability to be forced to the set or reset state (which
ignores the D and clock inputs), much like an SR flip-flop. Usually, the illegal S = R = 1
condition is resolved in D-type flip-flops. By setting S = R = 0, the flip-flop can be used as
described above. Here is the truth table for the others S and R possible configurations:

D Flip-Flop from NAND Latch

Clock

D Qnext

Rising
edge

Rising
edge

NonRising

D flip-flop
One of the main disadvantages of the basicsr nand gatebistable circuit
is that the indeterminate input condition of SET = logic 0 and
RESET = logic 0 is forbidden.
This state will force both outputs to be at logic 1, over-riding the
feedback latching action and whichever input goes to logic level 1 first
will lose control, while the other input still at logic 0 controls the
resulting state of the latch.
But in order to prevent this from happening an inverter can be
connected between the SET and the RESET inputs to produce
another type of flip flop circuit

D Flip-Flop from NAND Latch

That inverter is Known as adata latch,delay flip

flop,d-type bistable,d-type flip flopor just simply
aD flip flopas it is more generally called.
TheD flip flopis by far the most important of the
clocked flip-flops as it ensures that ensures that
inputsSandRare never equal to one at the same
time. The d-type flip flop are constructed from a
gatedSR flip-flopwith an inverter added between
theSand theRinputs to allow for a singleD(data)
input.
Then this single data input, labelledD, is used in place
of the set signal, and the inverter is used to
generate the complementary reset input thereby
making a level-sensitive d-type flip-flop from a levelsensitive rs-latch as nowS = DandR = not Das
shown.