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13.1

13.2

13.3

13.4

13.5

13.6

13.7

13.8

13.9

General Considerations

Emitter Follower as Power Amplifier

Push-Pull Stage

Improved Push-Pull Stage

Large-Signal Considerations

Short Circuit Protection

Heat Dissipation

Efficiency

Power Amplifier Classes

Cell phone needs 1W of power at the antenna.

Audio system needs tens to hundreds Watts of power.

Ordinary Voltage/Current amplifiers are not equipped for

such applications

Chapter Outline

Delivers large current levels.

Requires large voltage swings.

Draws a large amount of power from supply.

Dissipates a large amount of power, therefore gets hot.

Linearity

Power Efficiency

Voltage Rating

CH 13 Output Stages and Power Amplifiers

and resulting in a constant Vout.

CH 13 Output Stages and Power Amplifiers

Vout

1

Vin VT ln

I1 Vout

I S

RL

Vin 0.5V Vout 211mV

I C1

Vin VT ln

IC1 I1 RL

IS

I C1 0.01I1 Vin 390mV

introducing nonlinearity in I/O characteristics.

CH 13 Output Stages and Power Amplifiers

Push-Pull Stage

As Vin decreases, Q2 is on and pulls a current out of R L.

CH 13 Output Stages and Power Amplifiers

10

Vout=Vin+|VBE2| for large -Vin

For positive Vin, Q1 shifts the output down and for negative Vin,

Q2 shifts the output up.

CH 13 Output Stages and Power Amplifiers

11

However, for small Vin, there is a dead zone (both Q1 and Q2 are

off) in the I/O characteristic, resulting in gross nonlinearity.

CH 13 Output Stages and Power Amplifiers

12

either Q1 or Q2 is on.

When Vin is very small, the gain drops to zero.

CH 13 Output Stages and Power Amplifiers

13

For large Vin, the output follows the input with a fixed DC

offset, however as Vin becomes small the output drops to zero

and causes Crossover Distortion.

CH 13 Output Stages and Power Amplifiers

14

VB=VBE1+|VBE2|

With a battery of VB inserted between the bases of Q1 and Q2,

the dead zone is eliminated.

CH 13 Output Stages and Power Amplifiers

15

Implementation of VB

series.

I1 in figure (b) is used to bias the diodes and Q 1.

CH 13 Output Stages and Power Amplifiers

16

I in I1 I B1 I B 2

Iin

=> IB1=IB2

17

VD1VBE VoutVin

If I1=I2 & IB1IB2

Iin=0 when Vout=0

18

Addition of CE Stage

the bases of Q1 and Q2.

CH 13 Output Stages and Power Amplifiers

19

VA=0

Vout=0

IC1=[IS,Q1/IS,D1][IC3]

For bias point analysis, the circuit can be simplified to the one

on the right, which resembles a current mirror.

The relationship of IC1 and IQ3 is shown above.

CH 13 Output Stages and Power Amplifiers

20

Small-Signal Analysis

AV=-gm4(r1||r 2)(gm1+gm2)RL

Assuming 2rD is small and (gm1+gm2)RL is much greater than 1,

the circuit has a voltage gain shown above.

CH 13 Output Stages and Power Amplifiers

21

Rout

rO 3 || rO 4

1

g m1 g m 2 ( g m1 g m 2 )(r 1 || r 2 )

which will be problematic when driving a small resistance.

CH 13 Output Stages and Power Amplifiers

22

Example: Biasing

CE AV=5

Output Stage AV=0.8

RL=8

npn= 2pnp=100

IC1IC2

g m1 g m 2

g m1 g m 2 4

I C1 I C 2 6.5mA

r 1 || r 2 133

CH 13 Output Stages and Power Amplifiers

I C 3 I C 4 195 A

23

current, insufficient for high current operation (hundreds of mA).

CH 13 Output Stages and Power Amplifiers

24

Rout

2 1 g m3

combined with an NPN (Q2), providing a lower output resistance.

CH 13 Output Stages and Power Amplifiers

25

RL

1

vin vin

iin

1

r 3

1

g

2

m 3

rin 3 ( 2 1) RL r 3

CH 13 Output Stages and Power Amplifiers

26

to Q3 so the capacitance at the base of Q 2 can be

charged/discharged quickly.

CH 13 Output Stages and Power Amplifiers

27

Min Vin0

Vout|VEB2|

CH 13 Output Stages and Power Amplifiers

Min VinVBE2

Vout|VEB3|+VBE2

28

HiFi Design

higher fidelity.

CH 13 Output Stages and Power Amplifiers

29

Short-Circuit Protection

when the output is accidentally shorted to ground, preventing

short-circuit damage.

CH 13 Output Stages and Power Amplifiers

30

Pav I1 VCC

VP

2

a signal.

CH 13 Output Stages and Power Amplifiers

31

1 T

PI 1 I1 V p sin t VEE dt

T 0

PI 1 I1VEE

32

VP VCC VP

Pav

RL

4

Pav ,max

2

VCC

2

RL

CH 13 Output Stages and Power Amplifiers

33

VP VCC VP

Pav

RL

4

If Vp = 4VCC/ Pav=0

above supply (VCC)

CH 13 Output Stages and Power Amplifiers

34

Heat Sink

Heat sink, provides large surface area to dissipate heat from the chip.

35

I C1 I C 2

I D1I D 2

I S , D1I S ,D 2 I S ,Q1I S ,Q 2

currents in Q1 and Q2 will track those of D1 and D2 as long as

theie Iss track with temperature.

CH 13 Output Stages and Power Amplifiers

36

Efficiency

Pout

Pout Pckt

Emitter Follower

EF

EF

VP2

VP2 2 RL

2 RL I1 2VCC VP 2

VP

4VCC

I1=VP/RL

Push-Pull Stage

PP

PP

VP2

VP2 2 RL

2 RL 2 I1 VCC / VP 4

VPVCC

4

I1=VP/RL

divided by the power drawn from the supply

CH 13 Output Stages and Power Amplifiers

37

Example: Efficiency

Emitter Follower

VP=VCC/2

15

Push-Pull

I1=(VP/RL)/

VP

1

4 VCC VP

38

Class A and B

CH 13 Output Stages and Power Amplifiers

39

14.1

14.2

14.3

14.4

14.5

General Considerations

First-Order Filters

Second-Order Filters

Active Filters

Approximation of Filter Response

40

CH 14 Analog Filters

41

accompanies a signal, a filter is needed.

CH 14 Analog Filters

42

Filter Characteristics

Ideally, a filter needs to have a flat pass band and a sharp rolloff in its transition band.

Realistically, it has a rippling pass/stop band and a transition

band.

CH 14 Analog Filters

43

Example: Filter I

Design goal: Signal to Interference ratio of 15 dB

Solution: A filter with stop band of 40 dB

CH 14 Analog Filters

44

Example: Filter II

Design goal: Signal to Interference ratio of 20 dB

Solution: A filter with stop band of 60 dB at 60 Hz

CH 14 Analog Filters

45

adjacent Cellular and PCS signals.

CH 14 Analog Filters

46

Classification of Filters I

CH 14 Analog Filters

47

Classification of Filters II

Continuous-time

CH 14 Analog Filters

Discrete-time

48

Passive

CH 14 Analog Filters

Active

49

CH 14 Analog Filters

50

Filter b) has a transfer function with -40dB/dec roll-off, better

selectivity.

CH 14 Analog Filters

51

s Z1 s Z 2 L s Z m

H ( s)

s P1 s P2 L s Pm

CH 14 Analog Filters

Zm=mth zero

Pn =nth pole

52

Pole-Zero Diagram

CH 14 Analog Filters

53

Unstable

(no good)

CH 14 Analog Filters

Oscillatory

(no good)

Decaying

(good)

54

Imaginary Zero

CH 14 Analog Filters

55

Sensitivity

dP

P

SC

P

dC

C

P=Parameter

C=Component

variation of a filter component.

CH 14 Analog Filters

56

Example: Sensitivity

0 1 / R1C1

d0

1

2

dR1 R1 C1

d0

dR1

0

R1

S R10 1

CH 14 Analog Filters

57

First-Order Filters

s z1

H ( s)

s p1

First-order filters are represented by the transfer function

shown above.

Low/high pass filters can be realized by changing the relative

positions of poles and zeros.

CH 14 Analog Filters

58

R2 C2 < R 1 C1

CH 14 Analog Filters

R 2 C 2 > R 1C 1

59

CH 14 Analog Filters

60

Second-Order Filters

s2 s

H (s)

2 n

s

s n2

Q

p1,2

n

1

jn 1

2Q

4Q 2

equation with two complex poles shown above.

CH 14 Analog Filters

61

H ( j )

n2

CH 14 Analog Filters

==0

62

Q3

Q / 1 1/(4Q 2 ) 3

n 1 1/(2Q 2 ) n

CH 14 Analog Filters

63

2

s

H (s)

2 n

s

s n2

Q

CH 14 Analog Filters

==0

64

s

H (s)

2 n

s

s n2

Q

CH 14 Analog Filters

==0

65

R1L1s

Z2

R1L1C1s 2 L1s R1

CH 14 Analog Filters

66

L1s

Z1

L1C1s 2 1

An LC tank realizes a second-order band-pass filter with two

imaginary poles at j/(L1C1)1/2 , which implies infinite

impedance at =1/(L1C1)1/2.

CH 14 Analog Filters

67

Example: Tank

=, the capacitor acts as a short.

CH 14 Analog Filters

68

R1L1s

Z2

R1L1C1s 2 L1s R1

p1,2

L

1

1

j

1 21

2 R1C1

L1C1

4 R1 C1

implies there will be no infinite impedance at any .

CH 14 Analog Filters

69

Vout

ZP

( s)

Vin

ZS ZP

Low-pass

CH 14 Analog Filters

High-pass

Band-pass

70

Vout

R1

s

2

Vin

R1C1L1s L1s R1

CH 14 Analog Filters

71

Vout

R1

s

Vin

R1C1L1s 2 L1s R1

1

Q

2

CH 14 Analog Filters

Peaking exists

Voltage gain larger than unity

72

Good

Bad

than the circuit on the right.

CH 14 Analog Filters

73

Vout

L1C1R1s 2

s

Vin

R1C1L1s 2 L1s R1

CH 14 Analog Filters

74

Vout

L1s

s

Vin

R1C1L1s 2 L1s R1

CH 14 Analog Filters

75

Vout

1

s

Vin

R1R2C1C2 s 2 R1 R2 C2 s 1

1

Q

R1 R2

C

R1R2 1

C2

1

R1R2C1C2

particular filter implements a low-pass, second-order transfer

function.

CH 14 Analog Filters

76

Vout

s

Vin

CH 14 Analog Filters

R3

1

R4

R3

R1R2C1C2 s R1C2 R2C2 R1 C1 s 1

R4

77

C1=C2

R1=R2

CH 14 Analog Filters

78

S Rn

1

S RQ

1

S Rn

2

S RQ

2

SCn

1

SCn

2

R2C2

1

Q

2

R1C1

CH 14 Analog Filters

SCQ

1

SCQ

2

1

Q

2

S KQ QK

R1C1

R2C2

R2C2

R1C2

R1C1

R2C1

K=1+R3/R4

79

R1 R2 R

C1 C2 C

S RQ

1

S RQ

2

SCQ SCQ

1

S KQ

CH 14 Analog Filters

3 K

1

1

2 3 K

1

2

2 3 K

80

Q2

K 2

R2C2 3

S RQ 1

1

R1C1 4

R1C1 1

5

Q

SC

1

R2C2 8

4

S KQ

CH 14 Analog Filters

1.5

81

Integrator-Based Biquads

Vout

s2

s

Vin

2 n

s

s n2

Q

n 1

n2

Vout s Vin s . Vout s 2 Vout s

Q s

s

transfer functions.

The block-diagram above illustrates how.

CH 14 Analog Filters

82

KHN Biquads

n 1

n2

Vout s Vin s . Vout s 2 Vout s

Q s

s

R5

R6

1

R4 R5

R3

CH 14 Analog Filters

n

R4

1

.

Q R4 R5 R1C1

n2

R6

1

.

R3 R1R2C1C2

83

High-Pass

Vout

s2

s

Vin

s 2 n s n2

Q

Band-Pass

VX

s2

1

.

s

Vin

s 2 n s n2 R1C1s

Q

CH 14 Analog Filters

Low-Pass

VY

s2

1

.

s

2

Vin

s 2 n s n2 R1R2C1C2 s

Q

84

S Rn, R ,C ,C , R , R , R , R 0.5

1

S RQ , R

3

Q R3 R6

2 1 R5

R4

CH 14 Analog Filters

R2C2

R 3 R6 R1C1

S RQ , R ,C ,C 0.5

1

S RQ , R

4

5

R5

1

R4 R5

85

Tow-Thomas Biquad

Vout

RRR

C2 s

2 3 4.

Vin

R1

R2 R3 R4C1C2 s 2 R2 R4C2 s R3

Band-Pass

CH 14 Analog Filters

VY R3 R4

1

.

Vin

R1 R2 R3 R4C1C2 s 2 R2 R4C2 s R3

Low-Pass

86

1

R2 R4C1C2

Adjusted by R2 or R4

CH 14 Analog Filters

1

Q

R3

R2 R4C2

C1

Adjusted by R3

87

eliminated.

CH 14 Analog Filters

88

Z1Z 3

Z in

Z5

Z2Z4

It is possible to simulate the behavior of an inductor by using

active circuits in feedback with properly chosen passive

elements.

CH 14 Analog Filters

89

Zin

2

RX RY Cs

increases with frequency, simulating inductive effect.

CH 14 Analog Filters

90

Z1 Z 2 Z 3 RY

CH 14 Analog Filters

1

Z4

Cs

Zin RX RY2Cs

91

Vout

L1s 2

s

Vin

R1C1L1s 2 L1s R1

resembles a second-order high-pass filter.

CH 14 Analog Filters

92

CH 14 Analog Filters

RY

V4 Vout 1

RX

93

1

Z in

Cs RX Cs 1

Vout

Z in

1

Low-Pass

CH 14 Analog Filters

94

V4 Vout 2 RX Cs

Node 4 is no longer a scaled version of the Vout. Therefore the

output can only be sensed at node 1, suffering from a high

impedance.

CH 14 Analog Filters

95

transition band slope, one can create a filter template that will

lend itself to transfer function approximation.

CH 14 Analog Filters

96

Butterworth Response

H ( j )

1

1

0

2n

pass/stop bands at the expense of the transition band slope.

CH 14 Analog Filters

97

j

2k 1

pk 0 exp

exp j

, k 1, 2,L , n

2

2n

CH 14 Analog Filters

2nd-Order

nth-Order

98

f 2

f1

2n

64.2

f 2 2 f1

n=3

response on the left.

CH 14 Analog Filters

99

2

2

p1 2 *(1.45MHz ) * cos

j sin

3

3

2

2

p3 2 *(1.45MHz ) * cos

j sin

3

3

CH 14 Analog Filters

RC section

2nd-Order SK

p2 2 *(1.45MHz )

100

Chebyshev Response

H j

1

2

Cn

Chebyshev Polynomial

band response.

CH 14 Analog Filters

101

Chebyshev Polynomial

n=1,2,3

n=2,3

1

Cn cos n cos

, 0

CH 14 Analog Filters

cosh n cosh

, 0

102

H j

2

1 0.329 4 3

0

0

0=2 X (2MHz)

-18.7 dB a 2MHz.

CH 14 Analog Filters

103

Passband Ripple: 1 dB

Bandwidth: 5 MHz

Attenuation at 10 MHz: 30 dB

Whats the order?

1

2

1 0.509 cosh

CH 14 Analog Filters

n cosh 2

1

0.0316

n>3.66

104

pk 0 sin

2k 1 sinh

2n

2k 1 cosh 1 sinh 1 1

1

1 1

sinh

cos

0

2n

n

n

K=1,2,3,4

SK1

CH 14 Analog Filters

SK2

105

15.2 CMOS Inverter

15.3 CMOS NOR and NAND Gates

106

Chapter Outline

107

Inverter Characteristic

XA

An inverter outputs a logical 1 when the input is a logical 0

and vice versa.

CH 15 Digital CMOS Circuits

108

NMOS Inverter

Ron1

nCox

W

(VDD VTH )

L

M1 is in deep triode region. It produces V DD when M1 is off.

CH 15 Digital CMOS Circuits

109

However, practically the gain is finite.

CH 15 Digital CMOS Circuits

110

Transition Region: 50

mV

Supply voltage: 1.8V

Av

1.8

36

0.05

111

Since real power buses have losses, the power supply levels at

two different locations will be different. This will result in

logical level degradation.

CH 15 Digital CMOS Circuits

112

Supply B=1.675V

Supply A=1.8V

V 5 A 25m 125mV

CH 15 Digital CMOS Circuits

113

degradation in succeeding gates will reduce the output swings

of gates.

CH 15 Digital CMOS Circuits

114

transition region.

CH 15 Digital CMOS Circuits

115

can be above 1.

CH 15 Digital CMOS Circuits

116

Noise Margin

a gate can handle before the small-signal gain becomes -1.

CH 15 Digital CMOS Circuits

117

1: NM L VIL

1

VTH

W

nCox RD

L

1

W

2

Vout VDD nCox RD 2 Vin VTH Vout Vout

2

L

Vout

V V

in TH

W

2

2 nCox RD

L

Vin=VIH

2: NM H

VDD VIH

118

RD

19

nCox

W

VDD VTH

L

chosen above.

CH 15 Digital CMOS Circuits

119

nonlinearity, the concept of transfer function is no longer

meaningful. Therefore, we must resort to time-domain analysis to

evaluate the speed of a gate.

It usually takes 3 time constants for the output to transition.

CH 15 Digital CMOS Circuits

120

121

19 L2

RD C X

n VDD VTH

Assuming a 5% degradation in output low level, the time

constant at node X is shown above.

CH 15 Digital CMOS Circuits

122

Total Interconnect Capacitance: 15000X50x10 -18 =750 fF

Equivalent to 640 MOS FETs with W=0.5m, L=0.18m, C ox =13.5fF/m2

CH 15 Digital CMOS Circuits

123

Power-Delay Product

2

PDP VDD

CX

thought of as the amount of energy the gate uses in each

switching event.

CH 15 Digital CMOS Circuits

124

TPLH 3RD C X

2

PDP 3VDD

WLCox

CH 15 Digital CMOS Circuits

125

even when there is no switching.

RD presents a tradeoff between speed and power dissipation.

CH 15 Digital CMOS Circuits

126

pullup device that turns on when M1 is off and vice versa.

CH 15 Digital CMOS Circuits

127

Improved Falltime

the current from M1 is available to discharge the capacitor.

CH 15 Digital CMOS Circuits

128

CMOS Inverter

inverter shown above.

The NMOS/PMOS pair complement each other to produce the

desired effects.

CH 15 Digital CMOS Circuits

129

vout

g m1 g m 2 rO1 || rO 2

vin

When both M1 and M2 are in saturation, the small-signal gain is

shown above.

CH 15 Digital CMOS Circuits

130

Switching Threshold

when Vout equals Vin.

If VinT =Vdd/2, then W2/W1=n/p

CH 15 Digital CMOS Circuits

131

132

Example: VTC

W2

right.

CH 15 Digital CMOS Circuits

133

Noise Margins

NML =VIL

NMH =Vdd-VIH

VIL

a 1

a3

a 1

at which (Vout/ Vin)=-1

VIH

a 1

1 3a

a 1

at which (Vout/ Vin)=-1

W

L 1

a

W

p

L 2

134

VIL

a 1

a3

3

1

VIL VDD VTH 1

8

4

CH 15 Digital CMOS Circuits

135

NM H ,ideal NM L,ideal

VDD

2

136

Floating Output

VTH 1 VDD / 2

VTH 2 VDD / 2

When Vin=VDD/2, M2 and M1 will both be off and the output floats.

CH 15 Digital CMOS Circuits

137

saturation. However, as M 2 enters triode region the charge rate

becomes sublinear.

CH 15 Digital CMOS Circuits

138

enters triode, its current decreases.

CH 15 Digital CMOS Circuits

139

transition.

CH 15 Digital CMOS Circuits

140

is in saturation and becomes sublinear as M 1 enters triode region.

CH 15 Digital CMOS Circuits

141

TPLH

CL

2 VTH 2

W

VDD VTH 2

DD

TH 2

L 2

p Cox

V

ln 3 4 TH 2

VDD

TPHL

CL

W

VDD VTH 1

L 1

nCox

VTH 1

ln

3

VDD

VDD VTH 1

2 VTH 1

142

I AVG

1

W

p Cox VDD VTH 2

4

L 2

TPLH 2

CL

W

VDD VTH 2

L 2

p Cox

TPLH 2

CH 15 Digital CMOS Circuits

VDD VTH 2

4

Ron 2CL

3

143

1st Term

TPLH / HL

CL

W

VDD VTH 2 /1

L 2 /1

p / nCox

V

ln 3 4 TH 2 /1

VDD

VDD VTH 2 /1

2 VTH 2 /1

2nd Term

The sum of the 1st and 2nd terms of the bracket is the smallest

when VTH is the smallest, hence low VTH improves speed.

CH 15 Digital CMOS Circuits

144

Error

'

Ron1 || Ron

1

1

W W

'

L 1 L 1

2 RON 1

CH 15 Digital CMOS Circuits

145

1

2

PDissipation _ PMOS CLVDD

fin

2

2

Psupply CLVDD

fin

1

2

PDissipation _ NMOS CLVDD

fin

2

146

1

2

Estored CLVDD

2

1

2

Edissipated CLVDD

2

2

Edrawn CLVDD

CH 15 Digital CMOS Circuits

147

2

2 VTH 1

finCL2VDD

VTH 1

PDP

ln 3 4

W

V

V

V

DD

nCox VDD VTH 1 DD TH 1

L 1

Ron1=Ron2

148

Example: PDP

4

Ron

3

1

W

nCox VDD

L

2

7.25WL2Cox finVDD

PDP

n

CH 15 Digital CMOS Circuits

149

Crowbar Current

and there will be a current flowing from supply to ground.

CH 15 Digital CMOS Circuits

150

output will be low. Transistors operate as pull-down devices.

CH 15 Digital CMOS Circuits

151

and B is low, both M4 and M1 are on and produces an ill-defined

low.

CH 15 Digital CMOS Circuits

152

operate as pull-up devices.

CH 15 Digital CMOS Circuits

153

CMOS NOR

CMOS NOR.

CH 15 Digital CMOS Circuits

154

Vout A B C

'

W1=W2=W3=W

W4=W5=W6=6W

155

suffers from a high resistance, producing a long delay.

The widths of the PMOS transistors can be increased to counter

the high resistance, however this would load the preceding

stage and the overall delay of the system may not improve.

CH 15 Digital CMOS Circuits

156

CH 15 Digital CMOS Circuits

157

is high.

CH 15 Digital CMOS Circuits

158

CMOS NAND

Just like the CMOS NOR, the CMOS NAND can be implemented

by combining its respective NMOS and PMOS sections,

however it has better performance because its PMOS

transistors are not in series.

CH 15 Digital CMOS Circuits

159

Vout ABC

'

W1=W2=W3=3W

W4=W5=W6=2W

CH 15 Digital CMOS Circuits

160

parallel combination of A and B

series combination of A and B

the NMOS section by converting series combinations to the

parallel combinations and vice versa.

CH 15 Digital CMOS Circuits

161

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