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Lecture #14
CPLDs & FPGAs
Topics
CPLDs
FPGAs
Lect #14
Rissacher EE365
PLDs
16V8 (20 Pins)
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The OR gates
GAL16V8
(review seq_1.ppt)
Each output is
programmable as
combinational or
registered
Also has
programmable output
polarity
Lect #14
And Plane
XOR gates to
make inverting or
non-inverting buffer
Rissacher EE365
Rissacher EE365
CPLD Products
MAX 5000, 7000 & 9000
ATF & ATV
FLASH370, Ultra37000
ispLSI 1000 to 8000
XPLA
MACH 1 to 5
XC9500
URL
www.altera.com
www.atmel.com
www.cypress.com
www.latticesemi.com
www.philips.com
www.vantis.com
www.xilinx.com
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The number of I/O pins are much less than the total number of
Macrocells in family of devices
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Xinlinx CPLDs
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18 outputs
Global Clock
Global set/reset
18 Output
enable signals
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Architecture of Xilinx FB
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XC9500 Product
term allocator and
macrocell
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ISP
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Switch matrix
for XC95108
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FPGAs
Historically, FPGA architectures and
companies began around the same time as
CPLDs
FPGAs are closer to programmable ASICs - large emphasis on interconnection routing
Timing is difficult to predict -- multiple hops vs. the
fixed delay of a CPLDs switch matrix.
But more scalable to large sizes.
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Lect #14
Rissacher EE365
Lect #14
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FPGA specsmanship
Two flip-flops per CLB, plus two per I/O
cell.
25 gates per CLB if used for logic.
32 bits of RAM per CLB if not used for
logic.
All of this is valid only if your design has
a perfect fit.
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Detail
connections
controlled by
RAM bits
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Rissacher EE365
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Rissacher EE365
Next time
SRAM
DRAM
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