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Comments in Verilog
Commenting is important
your code
Some poor schmuck (perhaps you 4 years later) are going
to have to reference your code when a customer discovers a
bug.
Any moron who knows verilog can tell what the code is
doing.
Comment why (motivation/thought process) you are doing
that thing.
3
Commenting in Verilog
always @(posedge clk)
begin
Sig_FF1 <= Sig
Sig_FF2 <= Sig_FF1;
Sig_FF3 <= Sig_FF2;
end
Commenting in Verilog
always @(posedge clk)
/********************************************
* Sig is ansynchronous and has to be double flopped *
* for meta-stability reasons prior to use ************
*********************************/
begin
Sig_FF1 <= Sig;
Sig_FF2 <= Sig_FF1; // double flopped meta-stability free
Sig_FF3 <= Sig_FF2; // flop again for use in edge detection
end
/**********************************************
* Start bit in protocol initiated by falling edge of Sig line *
**********************************************/
assign start_bit = (~Sig_FF2 && Sig_FF3) ? 1b1 : 1b0;
Numbers in Verilog
Available bases:
Numbers in Verilog
Some Rules:
- Case sensitivity,
- Start with alphabetic charcter or an underscore,
- Can not start with a digit or a $
Need high
impedance
for modeling
of tri-state
busses
Meaning:
EEPROM
16
16
rd_ram
RAM
16
16
dbus[15:0]
rd_eep
d
CPU
clk
What value
does q have
prior to any
positive clock
edge?
It is unknown: x
(uninitialized)
10
OUT
OUT
B
0
1
1
x
z
x
z
OUT
0
1
1
X
X
1
1
OUT
T OUT
A
0
0
1
0
0
1
1
A
0
0
1
0
0
1
1
B
0
1
1
x
z
x
z
OUT
0
0
1
0
0
x
x
S
0
0
0
0
1
1
1
1
1
A
0
1
x
z
0
0
1
x
z
T
z
z
z
z
0
0
1
x
x
B
z
x
1
0
1
z
z
z
0
OUT
z
x
1
0
x
0
1
x
x
0 1 x z
A
OUT 1 0 x X
11
Meaning:
supply
strong
pull
weak
highz
High impedance
inv1
inv2
not
inv1 (Q,n1)
not (weak0,weak1) inv2 (n1,Q)
12
Registers in Verilog
Vectors in Verilog
///////////////////////////////////////////////////////////////
// State machine has 8 states, need a 3-bit encoding //
/////////////////////////////////////////////////////////////
reg [2:0] state,nxt_state;
Vectors in Verilog
module lft_shift(src,shft_in,result,shft_out);
input [15:0] src;
input shft_in;
output [15:0] result;
output shft_out;
shft_out
src
16
left shift
shft_in
16
result
/////////////////////////////////////////////////////////////////////////
// Can access 15 LSBs of src with [14:0] selector
//
// { , } is a process of concatenating two vectors to form one //
//////////////////////////////////////////////////////////////////////
assign result = {src[14:0],shft_in};
assign shft_out = src[15];
endmodule
15
addr1
addr2
RF
src1 = reg_file[addr1];
Flash
I2C
src1
src2
ALU
result
2b00;
2b01;
2b10;
case (state)
`idle : if (start_conv) nxt_state = `conv;
else
nxt_state = `idle
.
.
.
2b00;
2b01;
2b10;
case (state)
idle : if (start_conv) nxt_state = conv;
else
nxt_state = idlle
.
.
.
input X, Y ;
output S, C ;
input A, B, CI ;
output S, CO ;
endmodule
endmodule
20
endmodule
21
22
IN SIMULATION
IN REALITY
B
CI
majority
fa_bhv
CO
23
and, nand, or, nor, xor, xnor, not, buf, bufif1, etc.
Combinational building blocks for structural design
Known behavior
Cannot access inside description
Primitives
25
26
Hierarchy
Definition
Instantiation
Hierarchy
Primitives
Other modules (which may contain other modules)
xor
Add_full
Add_half
Add_half
and
xor
or
and
28
Add_half Module
Add_half
xor
and
29
Add_full Module
Add_full
Add_half
Add_half
or
wire [1:0] X;
wire W_n;
wire [3:0] word;
// instantiate decoder
dec_2_4_en DX (X, W_n, word);
Partial code instatiating decoder
34
wire [1:0] X;
wire W_n;
wire [3:0] word;
// instantiate decoder
dec_2_4_en DX (.A(X), .E_n(W_n),
.D(word));
Partial code instatiating decoder
35
General rules
Empty input ports => high impedance state (z)
Empty output ports => output not used
Specify all input ports anyway!
Z as an input is very badwhy?
endmodule
endmodule
37
endmodule
endmodule
38
blocks)
There are somethings you cant trust to synthesis, and need to
instantiate library gates structurally and use `dont touch directives for
synthesis.
Synthesis tools output structural verilog (gate level netlist). You need to be
able to read this output.
39
SYNTHESIS
Zero Delay:
Y and Z change
at same time
as A, B, and C!
Unit Delay:
Y changes 1 unit
after B, C
Unit Delay:
Z changes 1 unit
after A, Y
Unit Delay
Zero Delay
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Y
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
Z
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A B C
0 1 0
0 1 0
0 1 0
0 1 1
0 1 1
0 1 1
1 0 0
1 0 0
1 1 1
1 1 1
1 0 0
1 0 0
0 1 0
0 1 0
0 1 1
0 1 1
0 1 1
Y
x
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
1
Z
x
x
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
42
Types Of Delays
Delay Examples
wire #5 net_1;
wire #2 z_out;
and #3 (z_out, x_in, y_in);
wire #3 c;
assign #5 c = a & b;
01
1
B
n1
out
11
C
10
clk
A
clk
B
C
n1
out
45
01
1
B
11
n1
out
C
10
clk
46
NOR Gate:
Slow on rise
Fast on fall
Z
Z
A
B
NAND3 Gate:
Roughly equal
Rise/fall
C
47
Rise/Fall/Turn Off
in
out
in
in
out
out
Trise
not #(2,1) inv1(out,in);
in
out
Tfall
in
en
en
Referenced to
what the output
of the gate is
doing
out
Z
HiZ
Toff
bufif1 #(1,1,2) tri1(out,in,en);
Min/Typ/Max Delay
Min/Typ/Max
50
Design Flow
DUT Verilog
Code
Verilog
Testbenches
Bugs?
Modified
Testbenches
Verilog
Simulator
Verilog
Simulator
Yes
Gate Level
Struct .v
Yes
Yes
Bugs?
APR
Synth
script
Synthesis
Yes
SDF Files
layout
51