INPUT/ OUTPUT ORGANIZATION

UNIT-6

PERIPHERALS

11-1 Peripheral Devices

I/O Subsystem

Provides an efficient mode of communication between the central system and the
outside environment

Peripheral (or I/O Device)

Input or Output devices attached to the computer

Monitor (Visual Output Device) : CRT, LCD

KBD (Input Device) : light pen, mouse, touch screen, joy stick, digitizer
Printer (Hard Copy Device) : Dot matrix (impact), thermal, ink jet, laser (non-impact)
Storage Device : Magnetic tape, magnetic disk, optical disk

ASCII (American Standard Code for Information Interchange) Alphanumeric Characters

I/O communications are usually involved in the transfer of ASCII information

ASCII Code : Tab. 11-1
7 bit : 00 - 7F ( 0 - 127 )
80 - FF ( 128 - 255 ) : Greek, Italic, Graphics,

INPUT OUTPUT INTERFACE

1) A conversion of signal values may be required
2) A synchronization mechanism may be needed
The data transfer rate of peripherals is usually slower than the transfer rate of the
CPU

3) Data codes and formats in peripherals differ from the word format in the
CPU and Memory
4) The operating modes of peripherals are different from each other
Each peripherals must be controlled so as not to disturb the operation of other
peripherals connected to the CPU

Interface

Special hardware components between the CPU and peripherals

Supervise and Synchronize all input and output transfers

I/O Bus and Interface Modules

I/O bus
Data
Processor

I/O Bus
Data lines
Address lines
Control lines

Address
Control

Interface

Interface

Interface

Interface

Keyboard
and
display
terminal

Printer

Magnetic
disk

Magnetic
tape

Interface Modules (VLSI CHIP)

SCSI (Small Computer
System Interface)
IDE (Integrated Device
Electronics)
Centronics
RS-232
IEEE-488 (GPIB)

Integrated Device Electronics

I/O COMMAND
CONTROL

A Control
command is
issued to
activate the
peripheral and
to inform it
what to do.
EX :Magnetic Tape

STATUS

To test various
conditions in the
interface and the
peripheral. Ex.
Computer check
the status of the
peripheral before
a transfer is
initiated

DATA I/P

The interface
receives an
item of data
from the
peripheral and
places it in its
buffer register.

DATA
OUTPUT

The interface
to respond by
transferring
data from the
bus into one
of its registers

Memory Unit

Memory Bus

CPU
P
D

P
D

P
D

IOP
I/O BUS

P
D

I/O Bus versus Memory Bus

Computer buses can be used to communicate with memory and I/O
1) Use two separate buses, one for memory and the other for I/O :
I/O Processor
2) Use one common bus for both memory and I/O but have separate
control lines for each : Isolated I/O or I/O Mapped I/O
IN, OUT : I/O Instruction
Intel, Zilog
MOV or LD : Memory read/write Instruction
* Control Lines
I/O Request, Mem Request, Read/Write

Motorola

3) Use one common bus for memory and I/O with common control lines :
Memory Mapped I/O
MOV or LD : I/O and Memory read/write Instruction
* Control Lines
Read/Write

Example of I/O Interface

data bus

Chip select

Register select

I/O read

Bus
buffers

RS
1
RS
0
RD

I/O write

Timing
and
Control

WR

To CPU

RS
0

Port A register

Port B register

Control register

Status register

I/O data

Port B
register

I/O data

Control
register

Control

Status
register

Status

To I/O device

RS
1

CS

Port A
register

CS

Internal bus

Bidirectional

Register selected
None : data bus in high-impedance

4 I/O port :
Data port A, Data port B, Control, Status
Address Decode :
CS, RS1, RS0

Asynchronous Data Transfer

Synchronous Data Transfer

All data transfers occur simultaneously during the

occurrence of a clock pulse
Registers in the interface share a common clock
with CPU registers
Asynchronous Data Transfer

Internal timing in each unit (CPU and Interface) is

independent
Each unit uses its own private clock for internal
registers

Asynchronous Data Transfer

STROBE

Control signal to
indicate the time at
which data is being
transmitted

HANDSHAKING
The unit receiving the data
item responds with another
control signal to
acknowledge receipt of the
data.

TIMING DIAGRAM

Timing relationship that

must exist between
control signals and the
data in the buses.

Strobe Control
Strobe pulse is controlled by the clock pulses in the CPU.
CPU -always control of the buses and informs the external units how to transfer data.
Data transfer between an interface and an I/O device is commonly controlled by a set
of handshaking lines
Data bus
Source
unit

Strobe

Data bus
Destination
unit

Source
unit

(a) Block diagram

Data

Valid data

Strobe

Strobe
(a) Block diagram

Data

Valid data

Strobe
(b) Timing diagram

Source-initiated strobe

(b) Timing diagram

Destination-initiated strobe

Destination
unit

Data bus

Data valid

Source
unit

Destination
unit

Data valid

Source
unit

Data accepted

Destination
unit

Ready for data

(a) Block diagram

(a) Block diagram

independent units

Handshake : Agreement between two

Data bus

Data

Valid data

Ready for data

Data valid

Data valid

Data accepted

Data bus

(b) Timing diagram

Valid data

(b) Timing diagram

Source unit
Place data on bus
Enable data valid.

Destination unit

Source unit

Destination unit

Accept data from bus

Enable data accepted

Ready to accept
data.
Enable ready for data

Place data on bus

Enable data valid.
Disable data valid
Invalidate data on bus

Disable data accepted

Ready to accept data
(initial state)
(c) Sequence of events

Disable data valid

Invalidate data on bus
(initial state)

Accept data from bus

Disable reday for data

(c) Sequence of events

Cycle Diagram
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