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11.
FET
JFET
MOSFET (IGFET)
Enhancement
MOSFET
n-Channel
EMOSFET
p-Channel
EMOSFET
n-Channel JFET
p-Channel JFET
Depletion
MOSFET
n-Channel
DMOSFET
p-Channel
DMOSFET
SYMBOLS
Gate
Gate
Gate
Source
n-channel JFET
Drain
Drain
Drain
Source
n-channel JFET
Offset-gate symbol
Source
p-channel JFET
Figure: The nonconductive depletion region becomes broader with increased reverse bias.
(Note: The two gate regions of each FET are connected to each other.)
Operation of a JFET
Drain
N
Gate
+
Source
+
-
Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.
V
V
DS
P
GS
V
I
DS
DS
DSS
V2
P
V
V
GS
P
DSS
V2
P
V2
V V
DS
V
GS
P DS
2
V
V
DS
P
GS
2I
V
2
GS
and I
I
1
DS
DSS
V
Where, IDSS is the short circuit drain current, VP is the pinch off voltage
Figure: If vDG exceeds the breakdown voltage VB, drain current increases rapidly.
Saturation or Pinch
off Reg.
GS
I
I
1
DS
DSS
V
IDSS
VGS (off)=VP
V
1 GS
I I
DS
DSS
V
P
VGS
I DS I DSS 1
VP
VGS I DS RS 0
I DS
VGS
RS
GS
and I
I
1
DS
DSS
V
GS
I
1
DSS
V
GS
R
S
V
V
GS
GS
I
1
V
DSS
V
P
P
VGS
R 0
GS
I
1
DSS
V
GS
GS
and I
DS
RD
R1
io
is
ii
+
vs
ii
Rs
+
vs
RTh
Ci
vi
io
+
gmvp
rd
RD
RL
vo
_
_
s
vo
= -g m R 'L , where R 'L = rd R D R L
vi
A vs =
Zi =
vi
= R Th , where R Th = R 1 R 2
ii
AI =
Zo =
vo
io
AP =
= rd R D
seen by R L
Zi
vo
= A vi
vs
R s + Zi
io
= A vi
ii
Zi
RL
po
= A vi A I
pi
vo
R2
RSS
vi = vp
+
+
Co
RL
VDD
CSS
RD
R1
io
D
ii
ii
+
vs
_
vi
_
_
rd
io
RD
RL
vo
_
_
s
vo
= -g m R 'L , where R 'L = rd R D R L
vi
A vs =
Zi
vo
= A vi
vs
R s + Zi
Zi =
vi
= R Th , where R Th = R 1 R 2
ii
AI =
Z
io
= A vi i
ii
RL
Zo =
vo
io
AP =
po
= A vi A I
pi
= rd R D
seen by R L
vo
R2
RSS
+
gmvp
Ci
RL
vs
vi = vp
Co
Rs
+
RTh
VDD
CSS
2I
I D
= DSS
VGS - VP
VGS
VP2
gm =
I D
= K VGS - VT
VGS
(for EM MOSFET's)
3) Calculate the required values (typically Avi, Avs, AI, AP, Zi, and Zo. Use the formulas for
the appropriate amplifier configuration (CS, CG, CD, etc).
Example 7:
Find the mid-frequency values for Avi, Avs, AI, AP, Zi,
and Zo for the amplifier shown below. Assume that
Ci, Co, and CSS are large.
Note that this is the same biasing circuit used in Ex. 2,
so VGS = -0.178 V.
The JFET has the following specifications:
IDSS = 4 mA, VP = -1.46 V, rd = 50 k
18 V
500
800 k
io
D
ii
10 k
+
vs
Co
+
+
Ci
S
8k
vi
_
2k
vo
400 k
CSS
VDD
VDD
RD
R1
io
D
ii
CS
Co
Rs
Ci
RL
vs
vo
CSS
RSS
_
Common Source (CS) Amplifier
ii
S
+
-g m R
R 'L
rd R D R L
Zi
R Th
Zo
rd R D
io
Ci
G
vi
A vi
RD
RSS
RL
R1
_
C2
vo
_
R2
VCC
A vs
Common Gate (CG) Amplifier
VDD
VDD
AI
R1
AP
ii
Rs
+
vs
gmR
'
L
rd R D R L
R SS
1
gm
CD
g m R 'L
1 g m R 'L
R SS R L
R Th
Co
+
vs
'
L
R2
vi
_
Rs
CG
rd R D
R SS
1
gm
Zi
Zi
Zi
A vi
A
A
vi
vi
R
+
Z
R
+
Z
R
+
Z
i
i
i
s
s
s
Z
A vi i
RL
A vi A I
Z
A vi i
RL
A vi A I
Z
A vi i
RL
A vi A I
+
vi
Ci
Co
R2
R SS
where R Th = R1 R 2
io
_
Common Drain (CD) Amplifier (also called source follower)
+
RL
vo
_
Figure: n-Channel Enhancement MOSFET showing channel length L and channel width W.
Figure: For vGS < Vto the pn junction between drain and body is reverse biased and i D=0.
Figure: For vGS >Vto a channel of n-type material is induced in the region under the gate.
As vGS increases, the channel becomes thicker. For small values of vDS ,iD is proportional to vDS.
The device behaves as a resistor whose value depends on vGS.
Figure: As vDS increases, the channel pinches down at the drain end and iD increases more slowly.
Finally for vDS> vGS -Vto, iD becomes constant.
Current-Voltage Relationship of
n-EMOSFET
Figure: Diodes protect the oxide layer from destruction by static electric charge.
Figure: Simple NMOS amplifier circuit and Characteristics with load line.
Figure The more nearly horizontal bias line results in less change in the Q-point.
Figure FET small-signal equivalent circuit that accounts for the dependence of iD on vDS.
Analysis of CS Amplifier
A C Equivalent Circuit
Voltage gain, A
v
v i R g v
o
m gs
v
R
gs
L
Input imp., Z R R R
in
A o g R , R R r
v v
m L
L
D d
gs
r R
d D
r R
d
Av gm(rd || RD)
Zo rd || RD
Av gm(rd || RD)
Av gmRD, r 10R
d
Zi R1 || R2
Zo RD
rd 10RD
Figure vo(t) and vin(t) versus time for the common-source amplifier of Figure 5.28.
Figure vo(t) and vin(t) versus time for the common-source amplifier of Figure 5.28.
Figure Gain magnitude versus frequency for the common-source amplifier of Figure 5.28.
Figure Equivalent circuit used to find the output resistance of the source follower.
Figure Drain current versus drain-to-source voltage for zero gate-to-source voltage.
Figure Drain current versus vGS in the saturation region for n-channel devices.
Figure p-Channel FET circuit symbols. These are the same as the circuit symbols for n-channel devices,
except for the directions of the arrowheads.
Figure Drain current versus vGS for several types of FETs. iD is referenced into the drain terminal
for n-channel devices and out of the drain for p-channel devices.