Transmission Gate Based Circuits

Elmore Delay (HO)

Application of Elmore Delay to Mux Design (Ex.
7.4)
Logical Effort of CMOS Transmission Gate (
Dynamic D-Latch
Dynamic Logic
Distributed RC line as a lumped RC
Ladder
Lumped
NMOS TG as a D-Latch
CLK=1, Q=D
CLK=1 0, Q
last
is stored on C
2
CLK=0, high impedance state.

Problems with NMOS TG
1. Q can only rise to V
DD
-V
T
2. Clock feedthrough at Q when CLK goes low
3. The output stored in a high-Z stage after
CLK goes low is susceptible to all of the charge loss
mechanisms.
4.

is not available
CMOS TG as a latch
1. Q can only rise to V
DD
-V
T
2. Clock feed through at Q when CLK goes low
3. The output stored in a high-Z stage after
CLK goes low is susceptible to all of the charge
loss
mechanisms.
4.

is not available
CMOS TG with a

1. Q can only rise to V
DD
-V
T
2. Clock feed through at Q when CLK goes low
3. The output stored in a high-Z stage after
CLK goes low is susceptible to all of the charge
loss
mechanisms.
4.

is not available
Use feedback to statically hold the
logic value when the latch is off (1)
We can NOT drive a load from internal Q
Use feedback to statically hold the
logic value when the latch is off (2)
No Feedback when the latch is ON
Problem & Solution
CLK

Problem: If D and Q
prev
are different:
Driver + TG1 will drive Q to a different
value while INV2 and NMOS of TG2 will
drive Q to Q
prev

Solution: Size the forward path so that it is stronger than the feedback path.
Adjust V
S
Knob:
as defined in EQ. 4.15
Increase (W
N
L
P
)/(L
N
W
P
) Decreased V
S
.

Decrease (W
N
L
P
)/( L
N
W
P
) Increased V
S.


Increase W
P
to adjust V
S
W
N
/L
N
=200nm/200nm
W
P
/L
P
=200nm/200nm
W
N
/L
N
=200nm/200nm
W
P
/L
P
=460nm/200nm
Typical D-Latch Implementation in
CMOS
Typical D-Latch Implementation in
CMOS
CLK=1
1
0
Typical D-Latch Implementation in
CMOS
CLK=0
Q
prev
=1

1
0
Typical D-Latch Implementation in
CMOS
CLK

Q
now
=0
Q
prev
=1

1
0
Optional
Typical D-Latch Implementation in
CMOS
CLK

Q
now
=1
Q
prev
=0

0 1
Node X may have difficulty transitioning to 1 until
is 0.
Optional
Schematic of a TG Based D latch
Simulation of D-Latch
Zoom in to a transition
Positive Edge D Flip-flop
D is only transmitted to the output on the rising edge of CLK
Positive Edge D FF (CLK=0)
Positive Edge D FF (CLK=1)
Dynamic NAND
CLK=0 (Pre-Charged Phase)
NMOS is OFF. OUT is charged to VDD.

CLK=1 (Logic Evaluation Phase)
NMOS is ON.
If either A or B is GND, OUT=VDD.
If A=B=1, OUT=GND

Precharge Phase is only a small portion of the
clock cycle.

Disadvantage:
All dynamic logic circuits require a clock.
General Structure of a Dynamic Gate
Disadvantage:
All dynamic logic circuits require a clock
Examples
Example 7.6
P7.5 (a)
P7.5 (b)
Problem of Domino Logic Gates
1. During the precharge phase, the output voltage is high.
2. There is an active path to ground as soon as the foot transistor is turned on.
3. Once an output node has been discharged, it cannot go high until the next precharge
phase.
Solution
1. Define each stage as a dynamic gate plus an
inverter.
2. The output of each stage is now 0 during precharge.
Therefore all NMOS transistors are off during
precharge and can only be turned on during the
evaluation phase.
Disadvantage: An inverter can not be created!
Domino Cascaded Gates
During the pre-charge phase (=0), Y1, Y2 and Y3 are charged to VDD simultaneously.
=0 does not have to last very long since all stages are pre-charged simultaneously.
has a high duty cycle.
Note: There is no direct current from VDD to GND.
Exercise
c
b
a
clk
clk
V
DD
Out
X
Solution:
Out A BC
1. NMOS network implements
while X implements OUT.
2. The output of Inverter implements

Implement the expression
Out AB BC C
Solution
a
b
c
b
clk
clk
V
DD
Out
c
Propagation Delay of Domino
Cascaded Gates
The propagation delay is determined by:
1. The falling edge of the dynamic block
2. The rising edge of the inverter
Y
1
,Y
2
and Y
3
fall like dominos.
Improve the fall time of a Dynamic
Block
Design a domino stage with a stronger pull-
down.
Increase the sizes of NMOS devices.

c
b
a
clk
clk
V
DD
Out
The NMOS devices do not have to fight
with the pull up network. So the switch
voltage is lower. (VTN of the NMOS)
Static
Inverter
Domino
Gate
Improve the Rise Time of an Inverter
Design a static inverter with strong pull-up
Increase the size of the PMOS device.
Decrease W
N
L
P
/L
N
W
P
Increased V
s
of the inverter

Static
Inverter
Domino
Gate
Logical Effort Comparison
5/3
2/3 assuming that CLK is does not
arrive prior to either A or B
Dynamic NOR Gate
The Dynamic NOR gate is a faster circuit
because only one NMOS device is driven
The pull-down transistors do not fight with the
pull-up devices.
Limitations of Domino Logic
Charge Sharing
V
x
(initially)=0
V*=(C
out
)/(C
x
+C
out
)V
DD
Minimizing the effect of Charge
Sharing Using Keepers
The keepers keep VX at VDD and reduce
charge sharing to minimum. The keeper
transistor is weak enough (small W/L ratio
by using a large L) that when X=VDDGND.
NMOS can prevail over weak PMOS.

Disadvantage: large driver requirement of INV

Keepers
X
Enhancement
The INV sees a minimum length device.
The effective pull-up strength is controlled
by the long device.