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Objectives

Understand MOSFET operation.


Use the graphical load-line technique to
analyze basic FET amplifiers.
Analyze bias circuits.
Use small-signal equivalent circuits to
analyze FET amplifiers.
Objectives
Compute the performance parameters
of several FET amplifier configurations.
Select a FET amplifier configuration that
is appropriate for a given applications.
Understand the basic operation of
CMOS logic gates.
Transistors
These are three
terminal devices,
where the current or
voltage at one
terminal, the input
terminal, controls
the flow of current
between the two
remaining terminals.
Transistors
Can be classified as:
FET Field Effect Transistor;
Majority carrier device;
Unipolar device;
BJT Bipolar Junction Transistor;
Minority carrier device;
Bipolar device.
FETs
Two primary types:
MOSFET, Metal-Oxide-Semiconductor FET. Also
known as IGFET Insulated Gate FET;
JFET, Junction FET.
MOS transistors can be:
n-Channel;
Enhancement mode;
Depletion mode;
p-Channel;
Enhancement mode;
Depletion mode;
MOSFET Structure
Figure 12.1 n-channel enhancement MOSFET
showing channel length L and channel width W.
NMOS Symbol
Figure 12.2 Circuit symbol for an enhancement-
mode n-channel MOSFET.
Threshold Voltage V
to

The value of V
GS
where the drain
current just begins
to flow.
Typical values:
0.3 to 1.0 volts.
Operation in the Cutoff Region
Figure 12.3 For v
GS
< V
to
, the pn junction between
drain and body is reverse biased and i
D
= 0.

= for


Operation in the Triode(Ohmic) Region
Figure 12.4 For v
GS
> V
to
, a channel of n-type material is induced in
the region under the gate. As v
GS
increases, the channel becomes
thicker. For small values of v
DS
, i
D
is proportional to v
DS
. The device
behaves as a resistance whose value depends on v
GS
.
Operation in the Triode(Ohmic) Region
For

<

and




Conduction Parameter K
For =

where =

n
is the mobility of the electrons in the inversion layer.
C
ox
is the oxide capacitance per unit area.
KP is determined by the fabrication process.


Operation in the Saturation Region
Figure 12.5 As v
DS
increases, the channel pinches
down at the drain end and i
D
increases more slowly.
Finally, for v
DS
> v
GS
V
to
, i
D
becomes constant.
Operation in the Saturation Region
For

>

and





NMOS Characteristic Curves
Figure 12.6 Characteristic curves for an NMOS
transistor.
PMOS Symbol
Figure 12.8 Circuit symbol for PMOS transistor.
PMOS Characteristic Curves
Figure 12.9 Characteristic curves for a PMOS
transistor.
MOSFET Summary
Depletion Mode MOSFETs
n-Channel is built in.
V
GS
varies from
negative values to
positive values,
where negative
values of V
GS

depletes the channel
while positive values
enhance it further.

JFETs
Depletion-mode FET with a different structure than
that of the MOSFET.
Not generally used for switching elements of digital
circuits.
Used in special applications such as analog circuits
where very high input impedance is required.
JFETs
Every p-n junction has a depletion region
devoid of carriers, and the width of the
depletion region can be controlled by the
applied voltage across the junction.
JFETs
Note the highest
value of V
GS
.
What happens if you
make V
GS
positive
with respect to
ground.

Load Line Analysis
Figure 12.10 Simple NMOS amplifier circuit.

= sin 2000 +4


20 = 1k



Solve for:

= 0 and

= 0




Load Line Analysis
Figure 12.11 Drain characteristics and load line for
the circuit of Figure 12.10.

20 = 1k



Load Line Analysis
Bias Circuits
Figure 12.13 Fixed-plus self-bias circuit.

1
+
2
and

=

1

1
+
2

2

Bias Circuits
Figure 12.14 Graphical solution of Equations
12.12 and 12.13.
Exercise 12.5
Determine I
DQ
and V
DSQ

for the circuit shown in
Figure 12.16. The
transistor has:
KP = 50A/V
2

V
to
= 1V
L = 10m
W = 200m

Figure 12.16 Circuit for
Exercise 12.5.

Solution
Compute:
=


2
=
200m
10m
50A/V
2
2
= 0.5mA/V
2

1
+
2
= 20V
700K
1.3M+700K
= 7V
Given:

2

Then:

2


Solution

2
+
1

= 0
Substitute known values results in:

6 = 0
The roots are:

= 2V

= 3V (correct root)

Solution
Therefore:

2
= 2mA

= 16V


Small-Signal Equivalent Circuits


Figure 12.18 Illustration of the terms in Equation 12.15.
FETs Small-signal Equivalent Circuit
Figure 12.19 Small-signal equivalent circuit for
FETs.
Small-Signal Equivalent Circuits
Given:

2

Substituting:


We get:

2

Small-Signal Equivalent Circuits
Expanding expression:

2
+ 2

2


Reducing expression:

2
Q-points current cancels:

= 2

makes last term negligible:


= 2

(12.20)


Small-Signal Equivalent Circuits
Defining transconductance of the FET as:

= 2


Allows the current equation to be written as:

= 0

Transconductance Dependency
on Q-Point
Solving

2
for

and
substituting it into

= 2

= 2


Transconductance is proportional to the square root
of the Q-point drain current.

Substitute =


2
into

= 2

and verify
the relationship between transconductance and the
width-to-length ratio of the FET.
Dependence of i
D
on v
DS

Figure 12.20 FET small-signal equivalent circuit
that accounts for the dependence of i
D
on v
DS
.


Transconductance and Drain
Resistance as Partial Derivatives

=0

The condition

= 0 is equivalent to

remaining
constant at the Q-point, or

. Therefore we can
write:

and


Similarly:
1

and
1


Transconductance and Drain
Resistance as Partial Derivatives

=0

The condition

= 0 is equivalent to

remaining
constant at the Q-point, or

. Therefore we can
write:

and


Similarly:
1

and
1


Exercise 12.7
Find g
m
and r
d
for the characteristics of shown in
Figure 12.21 at the Q point of V
GSQ
= 2.5V and V
DSQ

= 6V.
Solution

=
4.41.1 mA
32 v
= 3.3mS
Similarly:
1

=
2.92.3 mA
142 V
= 0.05mS


1
0.05
= 20k
Small-Signal Equivalent Circuits


Figure 12.18 Illustration of the terms in Equation 12.15.
Common-source Amplifier.
Figure 12.22 Common-source amplifier.
Common-source Amplifier.

=
1
1

+
1

+
1

and

=
1

2

Common-source Amplifier.
Figure 12.24 Circuit used to find R
o
.

=
1
1

+
1


Source Follower
Figure 12.26 Source follower.
Source Follower

=
1
1

+
1

+
1

and

1+

=
1

2

Source Follower
Figure 12.28 Equivalent circuit used to find the
output resistance of the source follower..

=
1

+
1

+
1


Common-gate Amplifier
Figure 12.29 Common-gate amplifier.
Logic Gates
AND gate


OR Gate


Inverter

Logic Gates
NAND Gate




NOR Gate
CMOS Inverter
Figure 12.31 CMOS inverter.
Two-input CMOS NAND Gate
Figure 12.32 Two-input CMOS NAND gate.
Two-input CMOS NOR Gate
Figure 12.33 Two-input CMOS NOR gate.
Three-input CMOS NOR Gate
Figure 12.35 Three-input CMOS NOR gate.
(Answer for Exercise 12.15.)