FLIP FLOPS

1.Definition
2.Basic Flip Flop Types(SR,D,JK,T)
3.Conversion of 1 FF to Other



By: Sourabh Bhardwaj
Definition:
In electronics a flip-flop or latch is a circuit that
has two stable states and can be used to store
state information. The circuit can be made to
change state by signals applied to one or more
control inputs and will have one or two outputs.


It is the basic storage element in sequential logic.
Flip-flops and latches are a fundamental building block
of digital electronics systems used in computers,
communications, and many other types of systems.

Types Of Traditional Flip-Flops
SR
D
T
JK
The SET/RESET FLIP FLOP
Schematic Symbol
RS Flip-Flop

A RS-flip flop is the simplest possible memory element.
It is constructed by feeding the outputs of two NOR gates back to the other NOR gates input.
The inputs R and S are referred to as the Reset and Set inputs, respectively.
To understand the operation of the RS-flipflop (or RS-latch) consider the following scenarios:
S=1 and R=0: The output of the bottom NOR gate is equal to zero, Q'=0.
Hence both inputs to the top NOR gate are equal to one, thus, Q=1.
Hence, the input combination S=1 and R=0 leads to the flipflop being set to Q=1.
S=0 and R=1: Similar to the arguments above, the outputs become Q=0 and Q'=1.
We say that the flipflop is reset.
S=0 and R=0: Assume the flipflop is set (Q=0 and Q'=1), then the output of the top NOR
gate remains at Q=1 and the bottom NOR gate stays at Q'=0.
Similarly, when the flipflop is in a reset state (Q=1 and Q'=0), it will remain there with
this input combination.
Therefore, with inputs S=0 and R=0, the flipflop remains in its state.
S=1 and R=1: This input combination must be avoided.

R S Q Q' Comment
0 0 Q Q' Hold state
0 1 1 0 Set
1 0 0 1 Reset
1 1 ? ? Avoid


We can summarize the operation of the RS-flipflop by the following truth
table.
Note, the output Q' is simply the inverse of Q.
An RS flipflop can also be constructed from NAND gates.

Truth Table of S-R Flip-Flop
Clk S R Qn Qn+1
0 0 0 0 No Change
0 0 0 1 No Change
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0
Dont do
1 1 1 1
Characteristics Table Of SR Flip-Flop
S R Qn Qn+1 Operation
0 0 0 0 No-operation
0 0 1 1
0 1 0 0 RESET -
operation
0 1 1 0
1 0 0 1 SET operation
1 0 1 1
1 1 0 Dont do
1 1 1
Qn = before rising edge of CLOCK
Qn+1 = after rising edge of CLOCK
Excitation Table For The Clocked SR
Flip-Flop
Qn Qn+1 S R
0 0 0 Dont care
RESET but no
SET
0 1 1 0 Definite SET &
no RESET
1 0 0 1 Definite RESET
& no SET
1 1 0 Dont care SET
but no RESET
D Flip-Flop
Schematic Symbol of Clocked D Flip Flop
D-FLIP FLOP
An RS-flipflop is rarely used in actual sequential logic.
However, it is the fundamental building block for the very useful D-flipflop.
The D-flipflop has only a single data input.
That data input is connected to the S input of an RS-flip flop, while the inverse of D
is connected to the R input.
This prevents that the input combination ever occurs.
To allow the flipflop to be in a holding state, a D-flip flop has a second input called
``Enable.''
The Enable-input is AND-ed with the D-input, such that when Enable=0, the R and
S inputs of the RS-flipflop are 0 and the state is held.
When the Enable-input is 1, the S input of the RS flipflop equals the D input and R
is the inverse of D.
Hence, the value of D determines the value of the output Q when Enable is 1.
When Enable returns to 0, the most recent input D is ``remembered.''

Truth Table of Clocked D-Flip-Flop
Clk D Qn Qn+1
0 0 0 No Change
0 1 1 No Change
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Characteristics Table as well as TT
of D FF
D Qn Qn+1 Operation
0 0 0 RESET-operation
0 1 0
1 0 1 SET -operation
1 1 1
Qn = before rising edge of CLOCK
Qn+1 = after rising edge of CLOCK
Excitation Table For The Clocked D
Flip-Flop
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
The T Flip-Flop
Truth Table of T Flip-Flop
Clk T Qn Qn+1
0 0 0 No Change
0 1 1 No Change
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Characteristics Table of T FF
T Qn Qn+1 Operation
0 0 0 RESET-operation
0 1 1 SET -operation
1 0 1 SET -operation
1 1 0 RESET-operation
Qn = before rising edge of CLOCK
Qn+1 = after rising edge of CLOCK
Excitation Table For The Clocked T
Flip-Flop
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
The Clocked JK FLIP-FLOP
Truth Table of JK Flip-Flop
Clk J K Qn Qn+1
0 0 0 0 No Change
0 0 0 1 No Change
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0
1
1 1 1 1 0
Characteristics Table Of JK Flip-Flop
J K Qn Qn+1 Operation
0 0 0 0 Reset
0 0 1 1 Set
0 1 0 0 RESET
0 1 1 0 RESET
1 0 0 1 SET
1 0 1 1 SET
1 1 0 1 SET
1 1 1 0 RESET
Qn = before rising edge of CLOCK
Qn+1 = after rising edge of CLOCK
Excitation Table For The Clocked JK
Flip-Flop
Qn Qn+1 J K
0 0 0 Dont care K
but no J
0 1 1 Definite J &
Dont K
1 0 1 Definite K &
Dont care for J
1 1 0 Definite K= 0 &
Dont care for J
Design of Clocked Flip-Flop
Steps To Flip-Flop Design
STEP 1 : Given a Characteristic Table
prescribing some desired operation examine
each entry of this table (both inputs & output
desired), & answer the following question for
each row of the table:-
1) Does the cell need to be SET for this
condition, or would a SET cause the wrong
transition (SET or SET)?
Step to Flip-Flop Design
2) Does the cell need to be RESET for this
condition, or would a RESET cause the wrong
transition (RESET or RESET)?
3) Does the cell need to be left alone?
STEP2: Based on the answer to the questions
above & the resultant Truth-Table, plot a SET
MAP & RESET MAP & derive the
combinational logic for the SET/RESET
DECODER.
Designing of Clocked SR FF
CLK S R Qn Qn+1 SET RESET
0 0 0 0 0 0 No SET, RESET
0 0 0 1 1 0 SET, NO RESET
0 0 1 0 0 0
0 0 1 1 1 0
0 1 0 0 0 0 Input Can happen with no CLK
therefore optional
0 1 0 1 1 0
0 1 1 0 0 0
0 1 1 1 1 0
1 0 0 0 0 0
1 0 0 1 1 0
1 0 1 0 0 0
1 0 1 1 0 0 1 No SET, YES RESET
1 1 0 0 1 1 0 YES SET, NO RESET
1 1 0 1 1 0 SET, No RESET
1 1 1 0 Input conditions must not happen
1 1 1 1
Characteristic Table Truth Table For S & R
Decoder
Designing of Clocked SR Flip -Flop
From above table we will draw K-Map For SET
& RESET DECODER to get required Boolean
Expressions.