PRESENTED BY

JITHISH J
MVE13010
CONSTANT DELAY LOGIC
Introduction
Search continues for High Performance High
speed Logic
Dynamic Logic was implemented in 80s
But it too suffers from Charge Leakage, Reduced
Noise Margin
Dynamic Logic is proposed which achieve
Superior Perfomance

Static Logic
Always some mechanism to drive the output either high or
low
OR
Always a low-impedance DC path between the output and
either the supply voltage or the ground

Eg: CMOS inverter









Features
Does not require clock
The speed of the static CMOS circuit depends
on the transistor sizing
More area required to implement logic
2N number of transistors are required




Eg: For static Logic

CMOS

Pass Transistor Logic

Transmission Gate Logic

PseudoNMOS Logic





Dynamic Logic
Uses a sequence of precharge and conditional
evaluation phases
Not always a mechanism driving the output
high or low
Output is driven high or low during distinct
parts of the clock cycle
Temporary storage of signal values on the
capacitance of high-impedance circuit nodes


Eg:Dynamic AND Gate
Issues
Can be faster than static logic

Has minimum operating frequency

Fewer devices used to implement a given
logic

Problems with clock synchronization and
timing

Design is more difficult

Increases power consumption over static
CMOS



Solution-DOMINO Logic
Inserts ordinary static inverter between
stages

Clocked logic Eg:

Dynamic logic

Domino logic

NP Domino Logic

Compound Domino Logic

Feed Through logic(FTL)
During the high phase(Precharge) of CLK the
output node is pulled to ground through
transistor M2. When CLK becomes low
(Evaluation) the output node conditionally
evaluates to either logic high or low,
depending on the inputs to NMOS pull-down
network (PDN)


Cascaded Inverters-FTL Logic
INVERTER1 INVERTER2 INVERTER3

Plot of output voltages from 1-29 Inverters
Initial rise to VTH








Simulated Unwanted Glitch

Possible false
evaluation at even
number of gates

Disadvantages
FTL suffers from

Reduced noise margin

Excess direct path current( So More Power
Dissipation)

Nonzero nominal low output voltage

Unwanted Glitch



Dynamic FTL
DFTL eliminates the problem of false logic Evaluation

Inputs to FTLs NMOS PDN are always high when first entering the evaluation
period.

FTL gates enter Contention mode and conditionally make a low to high
transition depending on the inputs at evaluation period

Possible Improvements
Use a Customizable Timing Window to reduce
Active Power
Turns ON the circuit only during its switching
window
Use a Logic Block to eliminate glitch (and to
allow cascading)

Operation
Precharge and Evaluation
Precharge- When CLK low
Nodes X and Y pulled up
Evaluation- When CLK high
Contention mode
C-Q Mode
D-Q Mode

Timing Diagram
CD Logic
Critical Path for a 64 Bit Carry Merge Adder
Improvements
FTL- the contention lasts for the entire evaluation
period

TB effectively reduces CD logics
power consumption during the contention mode.

The local window technique in the proposed CD
gate allows
Customization of the window width for different
logic expressions

minimal power dissipation while not sacrificing
the performance.

Reduction in current
Performance Comparison
Less Delay=Faster Operation
Delay comparison of 8-Bit RCAs for various
logic styles

PDP vs Delay
Energy high
Performance comparison
Power Consumption High-Use only in timing critical path eg:Carry
Propogate path in an Adder

Conclusion
CD logic demonstrates superior performance,
especially
for complicated logic expressions
CD logic is approximately two times faster than
dynamic domino logic.
This is contributed by:
1) the pre-evaluated characteristic
2) the less number of transistors in the critical path
Suitable in a circuit where performance is the
primary concern
Reduced power consumption with the option of
optimizing individual gates window width

References
[1] S. Mathew, et.al Sub-500-ps 64-b ALUs in 0.18-
m SOI/Bulk CMOS: Design and Scaling Trends.
IEEE Journal of Solid-State Circuits, Vol. 36(11):
pp.1636-1646, November 2001.
[2] S. Mathew, M. Anders, R. Krishnamurthy and S.
Borkar A 4GHz 130nm Address Generation Unit with
32-Bit Sparse-Tree Adder Core. IEEE Journal of
Solid-State Circuits, Vol. 38(4): pp.689-695, May
2003.
[3] S. Mathew et.al A 4-GHz 300-mW 64-bit Integer
Execution ALU With Dual Supply Voltages in 90nm
CMOS. IEEE Journal of Solid-State Circuits, Vol.
40(1): pp.44-51, January 2005.
[4] S. Wijeratne et.al A 9-GHz 64-nm Intel Pentium 4
Processor Integer Execution Unit. IEEE Journal of
Solid-State Circuits, Vol. 42(1): pp.26-37, January
2007.
Thank you