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Synthesis of Sequential Machines

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Introduction
Study of Two Level logic Synthesis

Finite State Machine

Optimization Reducing the number of states and
assign binary codes.

Restrict on study of networks of machines.
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General Introduction
Digital electronics Circuits
Combinational Logic Ciruits
Sequential Logic Circuits
Combinational Logic
Basic element are Gates
Circuit Behavior: Output depends on the present input
Examples: Comparator, Arithmetic Circuits
Sequential Logic
Basic elements are Flip Flops and Latches
Further Classified into Synchronous and Asynchronous based on
the clock.
Circuit Behavior: Output depends on the past history.
Examples: Counters, Shift Registers.


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Classification of FSM
FSM Classification

Class A Machines / Mealy Machine
Class B Machine / Moore Machine
Class C Machine
Class D Machine
Class E Machine.

We restrict to Class A and Class B Machines.
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Class A / Mealy machine
Mealy Machine: M(S, I, O, , ) but
: S x I O (i.e. output depends on both present
state and present input)
for digital circuits, typically I = {0,1}m and
O = {0,1}n
In addition, (for both Moore and Mealy machines) certain
states are classified as reset or initial states
Finite automata are similar to FSMs, but
they do not produce any outputs,
they just accept input sequences (an accepting set
of states is given).

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Class A/Mealy Machine
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Class B /Moore Machine
Moore Machine: is a quintuple: M(S, I, O, , )
S: finite non-empty set of states
I: finite non-empty set of inputs
O: finite non-empty set of outputs
: S x I S transition (or next state) function
: S O output function (note: output only a
function of present state)

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Class B /Moore Machine
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Other Class Machine
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Simplified FSM Design Flow
Specification
State Minimization
State Encoding
Verification /
Testing
Logic/
Timing Optimization
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Steps Involved In Designing The FSM
1. Problem Analysis
2. Defining the Black Box
3. Draw the State Diagram (STG)/ASM
4. Draw the state Table/Flow table
5. Draw the State Transition Table
6. Draw the excitation Table
7. Using K-map/QM method find the output and
next state decoder function.
8. Implement the design.

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Example
Design an sequential circuit which detects the sequence
0101 continuously in the data sequence using D-FF.
Solution:
Black Box
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Step 2 State Diagram
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State Table
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State Transition Table
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Reduction Using K-map
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Reduction Using K-map
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Reduction Using K-map
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Implementation
CLK
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Moore Machine
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Moore Machine-State Table
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Moore Machine
Repeat the Steps as done for Mealy Machine.


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State Reduction
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State Reduction
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Incompletely Specified FSM
An FSM is incompletely specified if the
next state function and/or the output
functions are specified only for some
combinations of inputs and present states.
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Finite Automata
Similar to FSM whose task is only to
declare inputs accepted or rejected.
Classification
Deterministic
Non-deterministic

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State Equivalence and State Minimization
K-equivalence
Two State Si

and Sj, of Machine M are distinguishable
if and only if there exists at least one finite input
sequence which can be applied to M,causes different
output sequences, depending on whether Si and Sj is
the initial state.
If there exists for pair (Si,Sj) a distinguishing
sequence of length k,the states in (Si,Sj) are said to
be k-distinguishtable.

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Flow Table
PS NS,Z
X=0 X=1
A E,0 D,1
B F,0 B,0
C E,0 B,1
D F,0 B,0
E C,0 F,1
F B,0 C,0
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Contd..

states A and B are 1-distinguishable, since
a 1 input applied to A yields an output 1,
versus an output 0 from B.
states A and E are 3-distinguishable, since
input sequence 111 applied to A yields
output 100, versus an output 101 from E.

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Definition
States Si and Sj of Machine M are said to
be equivalent if and only if ,for every
possible input sequence, the same output
sequence will be produced regardless of
whether Si and Sj is the initial state.
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Minimization Procedure
Objective:
To describe a procedure for determining the
sets of equivalent states of as specified
machine M.

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Step One
Partition the states of M into subsets such
that all states in the same subset are 1-
equivalent.
Consider the example shown
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Example
PS NS,Z
X=0 X=1
A E,0 D,1
B F,0 D,0
C E,0 B,1
D F,0 B,0
E C,0 F,1
F B,0 C,0
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Minimization Procedure


P0=(ABCDEF)


0-distinguistablility





PS
NS,Z
X=0 X=1
A E,0 D,1
B F,0 D,0
C E,0 B,1
D F,0 B,0
E C,0 F,1
F B,0 C,0
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Minimization Procedure
P0=(ABCDEF)
P1=(ACE)(BDF)

1-equivalent
Obtained by
inspecting table and
placing those states
having same outputs
under all inputs, in the
same block.
PS
NS,Z
X=0 X=1
A E,0 D,1
B F,0 D,0
C E,0 B,1
D F,0 B,0
E C,0 F,1
F B,0 C,0
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Minimization Procedure
P0=(ABCDEF)
P1=(ACE)(BDF)
P2=(ACE)(BD)(F)

2-equivalent
Observed iff states
are 1-equivalent.


PS
NS,Z
X=0 X=1
A E,0 D,1
B F,0 D,0
C E,0 B,1
D F,0 B,0
E C,0 F,1
F B,0 C,0
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Minimization Procedure
P0=(ABCDEF)
P1=(ACE)(BDF)
P2=(ACE)(BD)(F)
P3=(AC)(E)(BD)(F)
P4=(AC)(E)(BD)(F)
PS
NS,Z
X=0 X=1
A E,0 D,1
B F,0 D,0
C E,0 B,1
D F,0 B,0
E C,0 F,1
F B,0 C,0
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In General
P
K+1
partition is obtained from P
K
by
placing in the same block of P
K
and whose
I
i
successors for every possible I
i
are also
common block of P
K
.
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Theorem
The equivalence partition is unique

If two states S
i
and S
j
of machine M are
distinguishable then they are
distinguishable by a sequence of length
n-1 or less ,where n is the number of
states in M.
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Machine equivalence


Two Machines M1 and M2 are said to be
equivalent iff for every state in M1,there is
a corresponding equivalent state in M2
and vice versa.
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Machine equivalence
P3=(AC)(E)(BD)(F)

(AC) s1
(E) s2
(BD) s3
(F) s4

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Reduced Flow Table
PS NS,Z
X=0 X=1
s1 s2,0 s3,1
s2 s1,0 s4,1
s3 s4,0 s3,0
s4 s3,0 s1,0
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Example
PS NS,Z
X=0 X=1
A E,0 D,1
B F,0 D,0
C E,0 B,1
D B,0 F,0
E C,0 F,1
F B,0 C,0
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State Equivalence
P
1
=P
0
={B
1
}={A,B,C,D,E,F}
X=0=> O
0
={0,0,0,0,0,0}
X=1=>O
1
={1,0,1,0,1,0}
P
1
1
={{A,C,E}{B,D,F}}
B1={B,D,F}
t
0
= {D,B,B} when x=0 => b
0
= {1,1,1}
t
1
={F,F,C} when x=1 => b
1
={1,1,2}
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State Equivalence
P
2
={{B,D},{F}}
B2={A,C,E} yield no refinement.
P
2
={{B,D},{F},{A,C,E}}
For k=3 first two blocks yield no refinement
B
3
={A,C,E}
t
0
={E,E,C} when x=0; b
0
={3,3,3}
t
1
={D,B,F} when x=1; b
1
={1,1,2}
P
3
={{B,D},{F},{A,C},{E}}

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State Equivalence
P
1
=P
0
={{A,B,C,D,E,F,G}}
O
0
=(0,0,0,0,1,0,0)
O
1
=(0,1,1,0,0,0,0)
P
1
={{A,B,C,D,F,G},{E}} when x=0 --- 1
P
1=
{{A,D,E,F,G}{BC}} when x=1 ---- 2
Refine=> 1 Intersection 2
P
1
={{A,D,F,G}{B,C}{E}}
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State Equivalence
Consider B1
t
0
={E,G,E,D} b
0
=(3,1,3,1) when x=0
t
1
={C,A,D,G} b
1
=(2,1,1,1) when x=1
Pb
0
={{A,F}{D,G}} Pb
1
={{A},{D,F,G}}
Refine P
2
={{A}{D,G}{F}}.
So P
2
={{A}{B,C}{D,G}{E}{F}}
III
larly
P
3
={{A}{B}{C}{D}{E}{F}{G}}

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Moore Machine
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Partition for a Moore Machine
Similar as done with Mealy Machine.
Imagine for the different inputs same output.
P
0
= (3,4,5,6)(1,2,7,8)
P
1=
(3,4,5,6)(1,2)(7,8)

a=(1,2) b=(3,4,5,6) c=(7,8)
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Iterative Collapsing Approach
Collapsed Flow table is constructed, in
which each occurrence of any member of
a given class as a next is replaced by its
representative.
One Checks if the partition P
1
is consistent
with the modified table ie all members of
each equivalence class must have
identical entries in the new flow table.
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Example
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Iterative Collapsed Method

P
1
={{A,D,F,G},{B,C},{E}}


We select representives A,B,E and
construct the collapsed flow table.

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This is not consistent, since rows A,D,F,G are not identical, although
rows D and G are and B and C are.
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Iterative Collapsed Method
The partition is refined into
P
2
= {{A},{B,C}{D,G}{E},{F}}
as before.

The next step is to collapse the original
table by replacing G by block 3
representive D and C by block 2
representive B.


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This flow table is still not consistent ,since rows D,G are not
identical,neither B,C.
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Iterative Collapsed Method
At this point the partition is refined to the
minimum partition ,which of course is
consistent ,so

P
3
= {{A},{B},{C},{D},{E},{F},{G}}