Advanced RISC Machines Advanced RISC Machines

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TM T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D
ARM
Advanced RISC Machines
Advanced RISC Machines
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TM 2 T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D
ARM Ltd
Founded in November 1990
Spun out of Acorn Computers

Designs the ARM range of RISC processor
cores
Licenses ARM core designs to semiconductor
partners who fabricate and sell to their
customers.
ARM does not fabricate silicon itself

Also develop technologies to assist with the
design-in of the ARM architecture
Software tools, boards, debug hardware,
application software, bus architectures,
peripherals etc
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ARM Partnership Model
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ARM Powered Products
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History of the ARM Processor
ARM1 ,ARM2 .. ARM 7
ARM9, ARM10 ,ARM11
CORTEX
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The ARM Core
What is meant by the core?
The core is the processing unit or the
computing engine.

It has all the computing power, and this
aspect is decided by the architecture,
which represents the basic design of the
processor.

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ARM provides hard and soft views to licencees
RTL and synthesis flows
GDSII layout
Licencees have the right to use hard or soft views of the IP
soft views include gate level netlists
hard views are DSMs
OEMs must use hard views
to protect ARM IP

Intellectual Property
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THE RISC ARCHITECTURE
These apply to most of the instructions
of ARM, but
not necessarily to all.
i) Instructions are of the same size, that
is, 32 bits
ii) Instructions are executed in one cycle
iii) Only the load and store instructions
access memory
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The ARM Microcontroller
It is ARM core with peripherals added to
it.
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13
14
15
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Features of ARM which make it special
Data bus width
Computational capability
Low Power
Pipelining
Multiple Register instructions
DSP Enhancements

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ARCHITECTURE
A large Uniform Register File
Load Store Architecture
Uniform and Fixed Length instructions
Good speed and low power consumption
High Code density
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ENHANCEMENT FROM RISC
Control over ALU and shifter over every
data processing instructions to maximize
their usage
Auto increment and auto decrement
addressing modes
Multiple load store instructions
Conditional execution of instruction to
maximize throughput
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Data items are placed in register file
Instructions use two source registers
and single destination register
Barrel shifter can preprocess the data
before going to ALU
Increment/Decrement logic update
register content to provide sequential
access independent of ALU
Core Data Path : Overview
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BARREL SHIFTER
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General purpose registers either hold data or Address
All registers:32 bit
In user mode 16 data registers and 2 status registers
are visible
Data registers r0-r15
r13,r14,r15 :special functions
r13 : Stack pointer
r14 : Link register
r15 :PC
REGISTERS
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When the processor is executing in ARM state:
All instructions are 32 bits wide
All instructions must be word aligned
Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as
instruction cannot be halfword or byte aligned).

When the processor is executing in Thumb state:
All instructions must be halfword aligned
Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as
instruction cannot be byte aligned).

When the processor is executing in Jazelle state:
Processor performs a word access to read 4 instructions at once
Program Counter (r15)
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Data Alignment
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Data Alignment
For word (32-bit ) the specified address
have its least significant 2 bits as 0
For half word (16-bit ) the specified
address have its least significant bit as 0
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CPSR :Current program Status register
SPSR : Saved Program Status register
STATUS REGISTERS
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Program Status Registers
Condition code flags
N = Negative result from ALU
Z = Zero result from ALU
C = ALU operation Carried out
V = ALU operation oVerflowed

Sticky Overflow flag - Q flag
Architecture 5TE/J only
Indicates if saturation has occurred

J bit
Architecture 5TEJ only
J = 1: Processor in Jazelle state

Interrupt Disable bits.
I = 1: Disables the IRQ.
F = 1: Disables the FIQ.

T Bit
Architecture xT only
T = 0: Processor in ARM state
T = 1: Processor in Thumb state

Mode bits
Specify the processor mode
27 31
N Z C V Q
28 6 7
I F T mode
16 23

8 15

5 4 0 24
f s x c
U n d e f i n e d J
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Processor mode determine
Access rights to CPSR
Which registers are active
Each processor mode is either
Privileged : Full read write access to the CPSR
Non-Privileged : Only read access to the control field
of CPSR but read write access to conditional flags
Processor Modes
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Processor Modes
The ARM has seven basic operating modes:

User : unprivileged mode under which most tasks run

FIQ : entered when a high priority (fast) interrupt is raised

IRQ : entered when a low priority (normal) interrupt is raised

Supervisor : entered on reset and when a Software Interrupt
instruction is executed

Abort : used to handle memory access violations

Undef : used to handle undefined instructions

System : privileged mode using the same registers as user mode
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Register File contains in all 37 registers
20 registers are hidden from program at different times
These registers are called Banked Registers
Banked Registers are available only
when the processor in a particular mode
Processors Mode other than system mode have a set
of banked register that are subset of 16 registers
Maps one-to-one onto a user mode register
Banked Registers
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r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr
FIQ IRQ SVC Undef Abort
User Mode
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr
Current Visible Registers
Banked out Registers
FIQ IRQ SVC Undef Abort
r0
r1
r2
r3
r4
r5
r6
r7
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr
User IRQ SVC Undef Abort
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
FIQ Mode IRQ Mode
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr
User FIQ SVC Undef Abort
r13 (sp)
r14 (lr)
Undef Mode
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr
User FIQ IRQ SVC Abort
r13 (sp)
r14 (lr)
SVC Mode
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr
User FIQ IRQ Undef Abort
r13 (sp)
r14 (lr)
Abort Mode
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r13 (sp)
r14 (lr)
spsr
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr
User FIQ IRQ SVC Undef
r13 (sp)
r14 (lr)
The ARM Register Set
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Register Organization Summary
User
mode
r0-r7,
r15,
and
cpsr
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr
FIQ
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
cpsr
r0
r1
r2
r3
r4
r5
r6
r7
User
r13 (sp)
r14 (lr)
spsr
IRQ
User
mode
r0-r12,
r15,
and
cpsr
r13 (sp)
r14 (lr)
spsr
Undef
User
mode
r0-r12,
r15,
and
cpsr
r13 (sp)
r14 (lr)
spsr
SVC
User
mode
r0-r12,
r15,
and
cpsr
r13 (sp)
r14 (lr)
spsr
Abort
User
mode
r0-r12,
r15,
and
cpsr
Thumb state
Low registers
Thumb state
High registers
Note: System mode uses the User mode register set
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Mode changes by writing directly to
CPSR or by hardware when the
processor responds to hardware or
interrupt
To return to USER MODE, a special
return instruction is used that instructs
the core to restore the original CPSR and
banked registers

Mode Changing
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SPSR present in every privileged mode
except system mode
Save the state of CPSR when the
privileged mode is entered so that the
user state is fully restored when the
process is resumed
SPSR
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INTERRUPT VECTOR TABLE
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TM T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D
Programming with Assembly
and C.
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Data Sizes and Instruction Sets
The ARM is a 32-bit architecture.

When used in relation to the ARM:
Byte means 8 bits
Halfword means 16 bits (two bytes)
Word means 32 bits (four bytes)

Most ARMs implement two instruction sets
32-bit ARM Instruction Set
16-bit Thumb Instruction Set

Jazelle cores can also execute Java bytecode
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Data Formats
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Instruction Set
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Manipulate data within registers
MOVE instructions
Arithmetic Instructions
Logical instructions
Comparison Instructions
Suffix S on data processing instructions
updates flags in CPSR

Data processing Instructions
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Operands are 32-bit wide come from
registers or specified as literals in the
instruction itself
Second operand placed in ALU via Barrel
shifter

Data processing Instructions
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MOV and MVN-Examples
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Shift and Rotate
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45
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Combining Mov and Shift
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Conditional Execution
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Arithmetic Instructions
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53
54
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Logical Instructions
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Compare Instructions
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Multiply content of a pair of registers
Long multiply generates 64 bit result
MUL r0,r1,r2
Contents of r1 and r2 multiplied and put in r0
UMULL r0,r1,r2,r3
Unsigned long multiply with result stored in
r0 and r1

Multiply Instructions
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Multiplication
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Multiplication -Examples
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Result of multiplication can be
accumulated with content of another
register
MLA Rd ,Rm,Rs,Rn
Rd =(Rm*Rs)+Rn
UMLAL Rdlo,Rdhi,Rm,Rs
[Rdlo,Rdhi] = [Rdlo,Rdhi,]+ (Rm*Rs)
Multiply and Accumulate
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Assembly Language
Programming
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Directives AREA and ENTRY-
Examples
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General Structure of an assembly
Language Line
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Directives for Defining data
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The EQU directive -Examples
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Constants allowed
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The RN directive-for naming
registers
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Assembly Programs
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Solution
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Branch Instructions
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Branch instruction usage -
examples
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Program for finding the factorial
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Division by repeated subtraction
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There is a form of the branch instruction
which is BL standing for
Branch and Link.
When a BL instruction is encountered,
the PC value is changed to that of the
target, but the old PC value is copied to
the LR register.
At the end of the procedure, the LR value
can be copied back to the PC.

Subroutines/Procedures using the Link register
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78
Solution
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Loading constants-immediate
mode
Constant specified in the instruction to be
copied to register or used as an operand
MOV r1,#0x7867
ADD r1,r2,#567
It is thus apparent that we cant have a 32-bit
constant embedded in the instruction.
80
Loading constants
So then what is the maximum size of the
constant that can be used in the
immediate mode?
We would like to be able to use
immediate constants as large as 32 bits.
ARM uses an ingenious technique, the
idea being the use of rotation of a small
number to generate a large number.

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Using the Barrel Shifter:
The Second Operand
* Immediate value
8 bit number
Can be rotated right through
an even number of positions.
Assembler will calculate
rotate for you from constant.
Register, optionally with
shift operation applied.
Shift value can be either
be:
5 bit unsigned integer
Specified in bottom byte
of another register.
Operand 1
Result
ALU
Barrel
Shifter
Operand 2
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Mechanism
12 bit for operand 2
12 bit modified as 8 bit immediate const
and 4 bit rotate operator
Maximum possible rotation 32 bits,hence
4bit rotate operand multiplied by 2 and
then rotated
8 bit shifted by even number positions
8 bit will become 32 bit during data
processing
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Generating a 32 bit constant
using rotation
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Generating a 32 bit constant
using rotation
86
87
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Second Operand :
Immediate Value (1)
There is no single instruction which will load a 32 bit immediate
constant into a register without performing a data load from
memory.
All ARM instructions are 32 bits long
ARM instructions do not use the instruction stream as data.
The data processing instruction format has 12 bits available for
operand2
If used directly this would only give a range of 4096.
Instead it is used to store 8 bit constants, giving a range of 0 -
255.
These 8 bits can then be rotated right through an even number of
positions (ie RORs by 0, 2, 4,..30).
This gives a much larger range of constants that can be directly loaded, though
some constants will still need to be loaded
from memory.
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Second Operand :
Immediate Value (2)
This gives us:
0 - 255 [0 - 0xff]
256,260,264,..,1020 [0x100-0x3fc, step 4, 0x40-0xff
ror 30]
1024,1040,1056,..,4080 [0x400-0xff0, step 16, 0x40-0xff ror 28]
4096,4160, 4224,..,16320 [0x1000-0x3fc0, step 64, 0x40-0xff ror 26]
These can be loaded using, for example:
MOV r0, #0x40, 26 ; => MOV r0, #0x1000 (ie 4096)
To make this easier, the assembler will convert to this form for us
if simply given the required constant:
MOV r0, #4096 ; => MOV r0, #0x1000 (ie 0x40 ror 26)
The bitwise complements can also be formed using MVN:
MOV r0, #0xFFFFFFFF ; assembles to MVN r0, #0
If the required constant cannot be generated, an error will
be reported.
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Transfers data between memory and
processor registers
Single register transfer (Signed and
unsigned words, half-words and bytes)
Multiple register transfer between memory
and processor in a single instruction
SWAP
swap content of a memory location with
register

Load Store Instructions
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LDR, LDRH,LDRB : Load
STR,STRH,STRB : Store
Boundary alignment
Supports different addressing modes
Register Indirect : LDR r0,[r1]
Immediate :LDR r0, [r1,#4]
12 bit offset added to the base register
Register operation : LDR r0,[r1,-r2]
Address calculated using base register and another
register

Single transfer Instructions
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Scaled
Address is calculated using base register and
barrel shifter
Pre and post indexing
Pre index with write back : LDR r0,[r1,#4]!
Updates the address base register with new
address
Post Index : LDR r0,[r1],#4
Updates the address register after address is
used
More addressing modes
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Load store multiple instructions transfer
multiple register contents between the memory
and the processor in a single instruction
More efficient for moving blocks of memory
and saving and restoring context and stack
Can increase Interrupt Latency
Usually these instruction execution are not
interrupted by ARM

Multiple register transfer
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Any subset of current bank of registers
can be transferred to memory or fetched
from memory
LDM
STM
The base register Rn determines the
source or destination

Multiple Byte Load Store
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Special case of load store instruction
SWP
SWB
SWAP instruction
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INDEXED ADDRESSING MODES
PRE INDEXED ADDRESSING MODE
LDR R0,[R7 ,#4].
STR R1, [R5,R6,LSL #2].
LDR R2,[R6 ,#-8] !
POST INDEXED ADDRESSING MODE
LDR R0,[R4],#4
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Load and Store Pre-indexed
Addressing

STR r0, [r1,#12]

r1
0x200
Base
Register
Memory
0x5
0x200
r0
0x5
Source
Register
for STR
Offset
12
0x20c
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Load and Store Post-indexed
Addressing

STR r0, [r1], #12

r1
0x200
Original
Base
Register
Memory
0x5
0x200
r0
0x5
Source
Register
for STR
Offset
12
0x20c
r1
0x20c
Updated
Base
Register
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MULTIPLE REGISTER LOAD AND
STORE
100
LDM{cond}address-mode Rn{!},reg-list{^}
{cond}
IA - increment after.
IB - increment before.
DA - decrement after.
DB -decrement before

101
LDMDA R0, {R4-R9}
STMIA R1,{R2-R4}
STMIA R1!,{R2-R4}
102
103
104
105
READONLY AND READ/WRITE
MEMORY
In readonly memory ,data is written using
directives like DCD,DCW
From there, it is copied to readwrite
memory using load and store
instructions

106
Literal Pools
LDR R1,= 0x33333333.

AREA PROG1,CODE,READONLY
ENTRY
LDR R1,=0x12400000
LDR R2,=0X00555555
ADD R3,R1,R2
LTORG
SPACE 4400
STOP B STOP
END
107
AREA STRIN1, CODE, READONLY
ENTRY

LDR R1, =SOURCE
LDR R0, =DESTIN
LDMIA R1,{R2-R8}
STMIA R0,{R2-R8}
STOP B STOP

SOURCE DCD 0x675889,0x1234568,0x9876543,0x2345678,0x8907653

AREA STRIN2,DATA,READWRITE ;define the R/W memory area
DESTIN DCD 0 ;
END

108
A stack is implemented as linear data
structure which grows up (ascending) or
down (descending)
Stack pointer hold the address of the
current top of the stack
STACK PROCESSING
109
Stacks
A stack is an area of memory which grows as new data is
pushed onto the top of it, and shrinks as data is
popped off the top.
Two pointers define the current limits of the stack.
A base pointer
used to point to the bottom of the stack (the first location).
A stack pointer
used to point the current top of the stack.
SP
BASE
PUSH
{1,2,3}
1
2
3
BASE
SP
POP
1
2
Result of
pop = 3
BASE
SP
110
Stack
Operation
Traditionally, a stack grows down in memory, with the last pushed value at
the lowest address. The ARM also supports ascending stacks, where the stack
structure grows up through memory.
The value of the stack pointer can either:
Point to the last occupied address (Full stack)
and so needs pre-decrementing (ie before the push)
Point to the next occupied address (Empty stack)
and so needs post-decrementing (ie after the push)
The stack type to be used is given by the postfix to the instruction:
STMFD / LDMFD : Full Descending stack
STMFA / LDMFA : Full Ascending stack.
STMED / LDMED : Empty Descending stack
STMEA / LDMEA : Empty Ascending stack
Note: ARM Compiler will always use a Full descending stack.
111
Stack Examples
STMFD sp!,
{r0,r1,r3-r5}
r5
r4
r3
r1
r0
SP
Old SP
STMED sp!,
{r0,r1,r3-r5}
r5
r4
r3
r1
r0
SP
Old SP
r5
r4
r3
r1
r0
STMFA sp!,
{r0,r1,r3-r5}
SP
Old SP
0x400
0x418
0x3e8
STMEA sp!,
{r0,r1,r3-r5}
r5
r4
r3
r1
r0
SP
Old SP
112
STACKS AND
SUBROUTINES/PROCEDURES

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