INTRODUCTION

TO
INTERFACING
 Computer interfacing
♦The art of connecting computers
and peripherals
♦It is not uncommon that you end up
removing all unnecessary hardware
from your computer to get that
communication device to work
 Computer interfacing
♦Despite all plug-and-play internal
hardware solutions for the PC,
connecting a number of external
devices still requires some amount
of technical knowledge and
experience
 Interfacing schemes
♦Programmed I/O
♦Interrupt Driven I/O
♦Direct memory access
 Program I/O
♦ The microcomputer executes a program to
communicate with an external device via
an I/O port
♦ Easy to use and modify, economical, slow
♦ Types of I/O ports
♦ Types of I/O addressing
 Types of I/O Ports
1. Each bit in the port can be individually
configured as either input or output

2. All the bits on the port can be set up as

either all parallel input or output bits
 Data Direction Register
♦ An out register and can be used to configure
the bits in the port as inputs or outputs
♦ Each port can be set up as input or output by
writing a “0” or a “1” in the corresponding bit
♦ A bidirectional buffer is connected at each bit
of the port
 Data Direction Register
♦ A “1” written to a particular bit enables
the output buffer
♦ A “0” enables the input buffer
7 6 5 4 3 2 1 0 bit position
0 0 1 1 0 1 0 0 DDR

I/O port

♦ You can connect LEDs to bit positions 2,4,5

♦ You can connect switches to bit positions 0,1,3,6,7
 I/O Addressing Techniques
1. Standard or Isolated I/O
2. Memory-mapped I/O
 Standard or Isolated I/O
♦ Uses the IO/M (IO/memory) pin on the
microprocessors chip
♦ The processor outputs a HIGH on this
pin to indicate the memory and the I/O
chips that an I/O operation is taking
place
♦ A LOW output from the processor to
this pin indicates a memory selection
 Memory-mapped I/O
♦ I/O ports are mapped into the
microprocessor’s main memory
♦ The MSB (most significant bit) of the address
may be used to distinguish between I/O and
memory
♦ If MSB of the address is “1”, an I/O port is
selected, otherwise, a memory location is
accessed
 Interrupt Driven I/O
♦ A scheme where an external device
requests the microcomputer to transfer
data by activating a signal on the
microcomputer’s interrupt line
♦ More difficult to use, faster (real time
system)
♦ Types of interrupts
 Types of Interrupts
♦External
♦Internal
♦Software
 External Interrupt
♦ Are initiated through the
microcomputer’s interrupt pins by
external devices
♦ Types of external interrupts
1. Maskable
2. Nonmaskable
 Maskable Interrupt
♦ Is enabled or disabled by executing
instructions such as EI or DI
♦ If it is disabled, the microcomputer
ignores the maskable interrupt
 Nonmaskable Interrupt
♦ It has higher priority than maskable
interrupt
♦ It is used as a power failure interrupt
 Internal Interrupt
♦ Activated internally by exceptional
conditions such as overflow, division by
zero, or execution of an illegal opcode
♦ The user writes a service routine to take
corrective measures and provide an
indication to inform the user that an
exceptional condition has occurred
 Software Interrupt
♦ Also known as system calls
♦ Normally used to call the operating
system
♦ It allows the user to switch from user to
supervisor mode
 DMA
♦ A scheme where data transfer is direct
between the external device and memory
bypassing the CPU.
♦ Mass data transfer, very fast. Examples
are disk drive, graphics, sound recording
systems etc.
♦ It uses a DMA controller chip for data
transfer operation
 DMA Controller Functions
1. The I/O devices request DMA
operation via the DMA request
lines of the chip
2. The chip activates the
microprocessor HOLD pin,
requesting the CPU to release the
bus
 DMA Controller Functions
3. The processor sends HLDA (hold
acknowledge) back to the chip,
indicating that the bus is disabled.
 Types of DMA
♦ Flyby DMA transfer
♦ Fetch-and-deposit DMA transfer
 Flyby DMA Transfer
♦ Also known as a single-cycle or single-
address transfer
♦ A single bus operation is used to
accomplish the transfer with data read
from the source and written to the
destination simultaneously
 Fetch-and-Deposit
♦ Also known as a dual-cycle, dual-
address, follow-through transfer
♦ The data being transferred is first read
from the I/O device or memory into a
temporary data register in the first cycle
♦ After that, the data is written to the
memory or I/O device in the next cycle
END