VLSI Design Lab

Presented By:
Parag Parandkar
Associate Professor, ECE Department,
Oriental University, Indore
Types of IC Designs
IC Designs can be Analog or Digital
Digital designs can be one of three groups
Full Custom
Every transistor designed and laid out by hand
ASIC (Application-Specific Integrated Circuits)
Designs synthesized automatically from a high-level
language description
Semi-Custom
Mixture of custom and synthesized modules

Need for transistors
Cannot make logic gates with voltage/current
source, RLC components
Consider steady state behavior of L and C
Need a switch: something where a (small)
signal can control the flow of another signal



Introduction to
CMOS VLSI
Design


CMOS Transistor Theory
Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (dV/dt) -> dt = (C/I) dV
Capacitance and current determine speed
Also explore what a degraded level really means
MOS Capacitor
Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
V
g
< 0
(b)
+
-
0 < V
g
< V
t
depletion region
(c)
+
-
V
g
> V
t
depletion region
inversion region
Terminal Voltages
Mode of operation depends on V
g
, V
d
, V
s

V
gs
= V
g
V
s
V
gd
= V
g
V
d
V
ds
= V
d
V
s
= V
gs
- V
gd
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence V
ds
> 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
V
g
V
s
V
d
V
gd
V
gs
V
ds
+
-
+
-
+
-
nMOS Cutoff
No channel
I
ds
= 0
+
-
V
gs
= 0
n+ n+
+
-
V
gd
p-type body
b
g
s
d
nMOS Linear
Channel forms
Current flows from d to s
e
-
from s to d
I
ds
increases with V
ds
Similar to linear resistor
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
= V
gs
+
-
V
gs
> V
t
n+ n+
+
-
V
gs
> V
gd
> V
t
V
ds
= 0
0 < V
ds
< V
gs
-V
t
p-type body
p-type body
b
g
s
d
b
g
s
d
I
ds
nMOS Saturation
Channel pinches off
I
ds
independent of V
ds
We say current saturates
Similar to current source
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
< V
t
V
ds
> V
gs
-V
t
p-type body
b
g
s
d
I
ds
I-V Characteristics
In Linear region, I
ds
depends on
How much charge is in the channel?
How fast is the charge moving?
Channel Charge
MOS structure looks like parallel plate
capacitor while operating in inversion
Gate oxide channel
Q
channel
=

n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate

Channel Charge
MOS structure looks like parallel plate
capacitor while operating in inversion
Gate oxide channel
Q
channel
= CV
C = C
g
= e
ox
WL/t
ox
= C
ox
WL
V = V
gc
V
t
= (V
gs
V
ds
/2) V
t

n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
C
ox
= e
ox
/ t
ox
Channel Charge
MOS structure looks like parallel plate
capacitor while operating in inversion
Gate oxide channel
Q
channel
= CV
C = C
g
= e
ox
WL/t
ox
= C
ox
WL
V =

n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
C
ox
= e
ox
/ t
ox
Channel Charge
MOS structure looks like parallel plate
capacitor while operating in inversion
Gate oxide channel
Q
channel
= CV
C = C
g
= e
ox
WL/t
ox
= C
ox
WL
V = V
gc
V
t
= (V
gs
V
ds
/2) V
t
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
C
ox
= e
ox
/ t
ox
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-
field between source and drain
v == mE m called mobility
E = V
ds
/L
Time for carrier to cross channel:
t = L / v

nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
ds
I =
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
channel
ds
Q
I
t
=
=
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
channel
ox
2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W
V
C V V V
L
V
V V V

|
=
| |
=
|
\ .
| |
=
|
\ .
ox
=
W
C
L
|
nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
ds
I =
nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
2
dsat
ds gs t dsat
V
I V V V |
| |
=
|
\ .
nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
( )
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V
|
|
| |
=
|
\ .
=
nMOS I-V Summary
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V
|
|

<

| |
= <
|
\ .

>

Shockley 1
st
order transistor models
Example
Example: a 0.6 mm process from AMI
semiconductor
t
ox
= 100
m = 350 cm
2
/V*s
V
t
= 0.7 V
Plot I
ds
vs. V
ds
V
gs
= 0, 1, 2, 3, 4, 5
Use W/L = 4/2 l
( )
14
2
8
3.9 8.85 10
350 120 /
100 10
ox
W W W
C A V
L L L
|

| | -
| |
= = =
| |

\ .
\ .
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
V
ds
I
d
s

(
m
A
)
V
gs
= 5
V
gs
= 4
V
gs
= 3
V
gs
= 2
V
gs
= 1
pMOS I-V
All dopings and voltages are inverted for
pMOS
Mobility m
p
is determined by holes
Typically 2-3x lower than that of electrons m
n
120 cm
2
/V*s in AMI 0.6 mm process
Thus pMOS must be wider to provide same
current
In this class, assume m
n
/ m
p
= 2

Capacitance
Any two conductors separated by an insulator
have capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion
Gate Capacitance
Approximate channel as connected to source
C
gs
= e
ox
WL/t
ox
= C
ox
WL = C
permicron
W
C
permicron
is typically about 2 fF/mm
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9c
0
)
polysilicon
gate
Diffusion Capacitance
C
sb
, C
db
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to C
g

for contacted diff
C
g
for uncontacted
Varies with process
Pass Transistors
We have assumed source is grounded
What if source > 0?
e.g. pass transistor passing V
DD
V
DD
V
DD
Pass Transistors
We have assumed source is grounded
What if source > 0?
e.g. pass transistor passing V
DD
V
g
= V
DD
If V
s
> V
DD
-V
t
, V
gs
< V
t
Hence transistor would turn itself off
nMOS pass transistors pull no higher than V
DD
-V
tn
Called a degraded 1
Approach degraded value slowly (low I
ds
)
pMOS pass transistors pull no lower than V
tp
V
DD
V
DD
Pass Transistor Ckts
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
Pass Transistor Ckts
V
DD
V
DD
V
s
= V
DD
-V
tn
V
SS
V
s
= |V
tp
|
V
DD
V
DD
-V
tn
V
DD
-V
tn
V
DD
-V
tn
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
-V
tn
V
DD
-2V
tn
Back to Introduction
Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): very many
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
Today: How to build your own simple CMOS
chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication
Rest of the course: How to build a good CMOS
chip

nMOS Transistor
Four terminals: gate, source, drain, body
Gate oxide body stack looks like a capacitor
Gate and body are conductors
SiO
2
(oxide) is a very good insulator
Called metal oxide semiconductor (MOS)
capacitor
Even though gate is
no longer made of metal
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
D
0
S
nMOS Operation Cont.
When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
D
1
S
pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (V
DD
)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
SiO
2
n
Gate Source Drain
bulk Si
Polysilicon
p+ p+
Power Supply Voltage
GND = 0 V
In 1980s, V
DD
= 5V
V
DD
has decreased in modern processes
High V
DD
would damage modern tiny transistors
Lower V
DD
saves power
V
DD
= 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,
Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to
drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF
CMOS Inverter
A Y
0
1
V
DD
A Y
GND
A Y
CMOS Inverter
A Y
0
1 0
V
DD
A=1 Y=0
GND
ON
OFF
A Y
CMOS Inverter
A Y
0 1
1 0
V
DD
A=0 Y=1
GND
OFF
ON
A Y
CMOS NAND Gate
A B Y
0 0
0 1
1 0
1 1
A
B
Y
CMOS NAND Gate
A B Y
0 0 1
0 1
1 0
1 1
A=0
B=0
Y=1
OFF
ON
ON
OFF
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0
1 1
A=0
B=1
Y=1
OFF
OFF
ON
ON
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1
A=1
B=0
Y=1
ON
ON
OFF
OFF
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
A=1
B=1
Y=0
ON
OFF
OFF
ON
CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
B
Y
3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
A
B
Y
C
CMOS Fabrication
CMOS transistors are fabricated on silicon
wafer
Lithography process similar to printing press
On each step, different materials are deposited
or etched
Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process
Inverter Cross-section
Typically use p-type substrate for nMOS
transistors
Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+ p+
SiO
2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
Well and Substrate Taps
Substrate must be tied to GND and n-well to
V
DD
Metal to lightly-doped semiconductor forms
poor connection called Shottky Diode
Use heavily doped well and substrate contacts
/ taps
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+ p+
substrate tap well tap
n+ p+
Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line
GND V
DD
Y
A
substrate tap
well tap
nMOS transistor pMOS transistor
Detailed Mask Views
Six masks
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO
2
(oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO
2
p substrate
Oxidation
Grow SiO
2
on top of Si wafer
900 1200 C with H
2
O or O
2
in oxidation furnace
p substrate
SiO
2
Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
p substrate
SiO
2
Photoresist
Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
p substrate
SiO
2
Photoresist
Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been
exposed
p substrate
SiO
2
Photoresist
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesnt melt in next step
p substrate
SiO
2
n-well
n-well is formed with diffusion or ion
implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO
2
, only enter exposed Si
n well
SiO
2
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of
steps
p substrate
n well
Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon
layer
Place wafer in furnace with Silane gas (SiH
4
)
Forms many small crystals called polysilicon
Heavily doped to be good conductor

Thin gate oxide
Polysilicon
p substrate
n well
Polysilicon Patterning
Use same lithography process to pattern
polysilicon

Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well
Self-Aligned Process
Use oxide and masking to expose where n+
dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-
well contact

p substrate
n well
N-diffusion
Pattern oxide and form n+ regions
Self-aligned process where gate blocks
diffusion
Polysilicon is better than metal for self-aligned
gates because it doesnt melt during later
processing
p substrate
n well
n+ Diffusion
N-diffusion cont.
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion

n well
p substrate
n+ n+ n+
N-diffusion cont.
Strip off oxide to complete patterning step
n well
p substrate
n+ n+ n+
P-Diffusion
Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact
p+ Diffusion
p substrate
n well
n+ n+ n+ p+ p+ p+
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+ n+ n+ p+ p+ p+
Contact
Metalization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires

p substrate
Metal
Thick field oxide
n well
n+ n+ n+ p+ p+ p+
Metal
Layout
Chips are specified with set of masks
Minimum dimensions of masks determine
transistor size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design
rules
Express rules in terms of l = f/2
E.g. l = 0.3 mm in 0.6 mm process
Simplified Design Rules
Conservative rules to get you started
Inverter Layout
Transistor dimensions specified as Width /
Length
Minimum size is 4l / 2l, sometimes called 1 unit
In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm
long
Summary
MOS Transistors are stack of gate, oxide, silicon
Can be viewed as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors

Now you know everything necessary to start
designing schematics and layout for a simple
chip!
MODULE
SYSTEM
LOGIC GATE
CIRCUIT
D Q
CMOS Inverter
ASIC
Full-Custom
FPGA
PLD
Cell-Based
Gate
Arrays

X
Combinational
Sequential
R
E
G
D
E
C
O
D
E
R

M
U
X
Simple
Basic
Complex
Static
Dynamic
Parallel
Connection
Series
Connection
p
n n + +
MOSFET
Bipolar
Diode
n p
n+ n+ p
DEVICE
Copy Right
August 2002
Maitham Shams
The MOSFET
Maitham Shams 2002
n+ n+
Gate Oxide
Source Drain
Body
p-substrate
Gate
2 Thin Oxide (SiO2)
)
Polycrystalline Silicon
or Polysilicon (conductor)
Lightly doped
Bulk Contact
Field
Oxide
p+ p+
Channel stop implant
or field implant
2 Thick Oxide (SiO2)
Heavily doped by
implantation or diffusion
For insulating
devices from
each other
Metal-Oxide-Semiconductor Field-Effect Transistor
Unipolar and symmetric device with four terminals of Gate, Source, Drain, and Body
NMOS: n-type Source and Drain, p-type Body connected to ground (GND)
PMOS: p-type Source and Drain, n-type Body connected to power supply (V
DD
)
CMOS Technology
Maitham Shams 2002
PMOS NMOS
p+
n+
n+
p-substrate
p+
contact cut
Polysilicon
n-well
Metal
Gate oxide
Complementary Metal Oxide Silicon Technology combines NMOS and PMOS
Mainstream IC Technology
in
Foreseeable Future
High Integration
Density
Simple Processing
Steps
Low Power
Consumption
Adequate Speed
High Reliability
MOSFET Types and Symbols
Maitham Shams 2002
D
G
S
D
G
S
D
G
S
D
G
S
B
Analog Digital
With non standard
substrate connection
Enhancement PMOS Depletion PMOS
I
DS
V
GS
+V
Tp
0
I
DS
V
GS
-V Tp
0
D
G
S
D
G
S
D
G
S
B
D
G
S
Analog Digital
With non standard
substrate connection
Enhancement NMOS
Depletion NMOS
I
DS
V
GS +V
Tn
0
0
I
DS
V
GS
-V
Tn
Enhancement mode transistors are normally OFF (non-conducting with zero bias)
Depletion mode transistors are normally ON (conduct with zero bias)
Most CMOS ICs use Enhancement type MOS