ASMD based Design: UART Transmitter

Agenda of Lecture
2
UART Basics
Design Partitioning of UART TX
Control Unit and Its ASMD
UART TX, Putting it All Together

Purpose of this Lecture is not to go through UART or To learn it.
Infact this Lecture is insight of ASMD based designs, how you
can think a design, Draw the ASMD and Write the code of the
ASMD. Take this Lecture as thinking Point of ASMD designs.


1- UART Basics
1. UART (Universal Asynchronous Receiver
Transmitter) Performs serial communication
between UART and other components.
2. UART takes a Byte of Data in Parallel converts
it into serial form and includes Stop, Start
and Parity Bits with the data.
3. The UART transmission is controlled by the
Clock specially controlled with accordance to
the Baud Rate.
Serial Communication
Steps for ASMD design Methodology
1. Draw a Block Diagram of the Design given on
Side 6.
2. Partition the design into control unit and Data
Path as on Slide-6. Connect all inputs to Control
unit and all output to Data Path.
3. Start thinking about possible components in the
Data path and Signals associated with them.
4. Figure out Control Signals from the Data Path
Signals.
5. Plan States of Control Unit and Draw its ASMD of
the Control Unit.

2- Design Partitioning of UART TX

Partition the design into Control Unit and Data Path Connect all inputs to the
Control Unit and out puts to Data Path.
Possible Data Path components
A 8-Bit register needed to buffer the data.
A Counter which can count from 0 to 9. When
the counter will complete its counting cycle
this will ensure that Serial data has been
transmitted.
A shift register which can shift the bit out one
by on each transact of the Clock.
A parity calculator which generates one bit
parity when the 8-bit data is given to it.

Possible Data Path components
Possible Data Path components
Connecting Data path and Control Unit
3- Control Unit Design
1. RST_TXReg, RST Counter and RST_Dreg can reset the
respective components.
2. LD_Dreg enables loading data into Data_Reg.
3. LD_TxReg will load parity Data, Data from Data_Reg .
4. Shift_TxReg Will control Shifting operation of Tx_Reg.

ASMD of Control Unit
Simulation of Control Unit
4- UART Transmitter: Putting it All
Together
1. The host Initially send data on Data_In and assert Data_Ready to tell UART_TX the new
data is available.
2. The Data Loaded by Host will remain in Buffer of UART_TX unit Data_Send is not asserted.
Host raise Data_Send to Tell UART Transmitter to send data out one by one.


UART Transmitter Working, Loading Data
1. The Host Loads the Data by giving data in Data_In and Asserting
Data_Ready Signal.
2. The Control Unit Generate LD_Dreg, Data path loads data seeing this
signal.


UART Transmitter Working, Ready to Transmit
1. The Host Asserts Data_Send to tell Design to Send the Data now.
2. Control Unit Asserts LD_TxReg after seeing Data_Send. This signal loads
Data from Data_Reg into TX_Reg and Parity from Pout.

UART Transmitter, Transmitting
1. In the Next Clock Cycle Shift_TxReg is asserted by Control Unit. This Enable
counter.
2. The first bit of TX_Reg becomes one which is tied to the output. This send
Start bit.
UART Transmitter, Transmitting
1. On each Clock Cycle TX_Reg is shifted one by one insert 1 from Left hand
side. Bit by Bit 8 Clock Cycles send all the data serially out.
2. Cflag of Counter is raised when counter counts 9. At this time all the bits are
transmitted. And Shift_TxReg is deasserted.
UART Transmitter, Simulation